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[ak4636] ms1012-e-01 2010/08 - 1 - general description the ak4636 is a 16-bit mono codec with micr ophone-amplifier, speaker-amplifier and video- amplifier. input circuits incl ude a microphone-amplifier and an alc (aut omatic level control) circuit. output circuits include a speak er-amplifier and mono line output. video circuits include a lpf and video-amplifier. the ak4636 suits a video recording/ playback system of digital still cameras. the ak4636 is housed in a space-savi ng 29-pin csp 2.5mm x 3.0mm pa ckage (ak4636ecb) or a 32pin qfn 4.0mm x 4.0mm package (AK4636EN). feature 1. 16-bit delta-sigma mono codec 2. recording function ? 1ch mono input ? mic amplifier: (0db/+3db/+6db/+10db/ +17db/+20db/+23db/+ 26db/+29db/+32db) ? digital alc (automatic level control) - output noise suppression - setting rate (+36db -54db, 0.375db step, mute) ? adc performance (mic-amp=+20db) - s/(n+d): 83db - dr, s/n: 85db ? wind-noise reduction filter ? 5 band notch filter ? digital microphone interface 3. playback function ? digital alc (automatic level control) - output noise suppression - setting rate (+36db -54db, 0.375db step, mute) ? mono line output: - s/(n+d): 84db - s/n: 90db ? mono speaker-amp - s/(n+d): 60db (150mw@8 ) - btl output - output power: 400mw @ 8 (svdd=3.3v) ? beep generator 4. video function ? a composite video input ? gain control (-1.0db +10.5db, 0.5db step) ? low pass filter ? a video-amp for composite video signal ? dc direct output 5. power management 6. pll mode: ? frequencies: 11.2896mhz, 12mhz, 13.5mhz, 24m hz, 27mhz (mcki pin) 1fs (fck pin) 16fs, 32fs or 64fs (bick pin) 7. ext mode: ak4636 16-bit mono codec with alc & mic/spk/video- a mp
[ak4636] ms1012-e-01 2010/08 - 2 - ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 8. sampling rate: ? pll slave mode (fck pin): 7.35khz ~ 48khz ? pll slave mode (bick pin): 7.35khz ~ 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext slave mode / ext master mode: 7.35khz ~ 48khz (256fs), 7.35khz ~ 26khz (512fs), 7.35khz ~ 13khz (1024fs) 9. output master clock frequency: 256fs 10. serial p interface: 3-wire, i 2 c bus (ver 1.0, 400khz high speed mode) 11. master / slave mode 12. audio interface format: msb first, 2?s complement ? adc: dsp mode, 16bit msb justified, i 2 s ? dac: dsp mode, 16bit msb justif ied, 16bit lsb justified, i 2 s 13. ta = - 30 85 c 14. power supply ? analog supply (avdd): 2.6 3.6v ? digital supply (dvdd): 1.6 3.6v ? speaker supply (svdd): 2.6 3.6v ? video supply (vvdd): 2.8 3.6v 15. package: ak4636ecb ? 29pin csp (2.5mm x 3.0mm, 0.5mm pitch) AK4636EN ? 32pin qfn (4.0mm x 4.0mm, 0.4mm pitch) block diagram mic power supply a/d hpf1 pm mp pmadc or pmdm mpi/dmp mic/micp/dmdat avdd vss1 vcom dvdd bick fck sdto sdti vss2 mic- a mp 0db /+3db/+6db/+10db/+17db/+20db/ +23db/+26db / +29db / +32db mi c 4 band eq vol (alc) pmpfil pll pmpll control register cclk/scl cdtio mc ko mcki vcoc csn/sda lpf hpf2 lin/micn/dmclk pdn svdd vss3 vou t pmv composite video out +6db gca lp f -1db ~ +10.5db step 0.5db clamp vin pmdac line out speaker spp spn pmao aout vvdd beep ge nerato r eq smu te datt d/a pmspk spk-amp i2c pmbp beep audio i/f figure 1. ak4636 block diagram
[ak4636] ms1012-e-01 2010/08 - 3 - ordering guide ak4636ecb ? 30 +85 c 29pin csp (2.5mmx3.0mm 0.5mm pitch) AK4636EN ? 30 +85 c 32pin qfn (4.0mmx4.0mm 0.4mm pitch) akd4636 ak4636ecb evaluation board pin layout ak4636ecb a bc e d 6 5 3 4 1 2 top view 6 pdn dvdd vss2 spp svdd 5 sdto mcko sdti vss3 spn 4 bick mcki fck aout beep 3 cclk/scl cdtio i2c mic/micp/ dmdat lin/micn/ dmclk 2 csn/sda vout vvdd vcom mpi/dmp 1 vin vss1 avdd vcoc a b c d e top view
[ak4636] ms1012-e-01 2010/08 - 4 - AK4636EN nc nc vss3 beep aout lin/ micn/ dmclk mic/ micp/ dmdat mpi/ dmp spn svdd spp nc vss2 dvdd mcko pdn vcom vcoc avdd vss1 vvdd vout vin i2c sdto sdti bick mcki fck cclk/ scl cdtio csn/ sda AK4636EN top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8
[ak4636] ms1012-e-01 2010/08 - 5 - pin/function ak4636ecb no. pin name i/o function d2 vcom o common voltage output pin = 1.15v(typ) bias voltage of adc inputs and dac outputs. e1 vcoc o output pin for loop filter of pll circuit this pin must be connected to vss1 with one resistor and capacitor in series. d1 avdd - analog power supply pin c1 vss1 - ground pin c2 vvdd - video amp power supply pin b2 vout o composite video signal driver pin a1 vin i composite video signal input pin c3 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial csn i chip select pin (i2c pin = ?l?) a2 sda i/o control data input/output pin (i2c pin = ?h?) b3 cdtio i/o control data input/output pin (i2c pin = ?l?) this pin must be connected to the ground. (i2c pin = ?h?) cclk i control data clock pin (i2c pin = ?l?) a3 scl i control data clock pin (i2c pin = ?h?) c4 fck i/o frame clock pin b4 mcki i external master clock input pin a4 bick i/o audio serial data clock pin c5 sdti i audio serial data input pin a5 sdto o audio serial data output pin a6 pdn i power-down & reset when ?l?, the ak4636 is in power-down mode and is held in reset. the ak4636 must be always reset upon power-up. b5 mcko o master clock output pin b6 dvdd - digital power supply pin c6 vss2 - ground pin. d6 spp o speaker amp positive output pin e6 svdd - speaker amp power supply pin e5 spn o speaker amp negative output pin e4 beep i beep signal input pin d5 vss3 - ground pin d4 aout o mono line output pin lin i line input pin for single ended input (mdif bit = ?0?, dmic bit = ?0?) micn i microphone negative input pin for differential input (mdif bit = ?1?, dmic bit = ?0?) e3 dmclk i digital microphon clock pin (dmic bit = ?1?) mic i microphone input pin for single ended input (mdif bit = ?0?,dmic bit = ?0?) micp i microphone positive input pi n for differential input (mdif bit = ?1? dmic bit = ?0?) d3 dmdat o digital microphone data input pin (dmic bit = ?1?) mpi o mic power supply pin for microphone (dmpe bit = ?0?) e2 dmp o mic power supply pin for digital microphone (dmpe bit = ?1?)
[ak4636] ms1012-e-01 2010/08 - 6 - AK4636EN no. pin name i/o function 1 vcom o common voltage output pin = 1.15v(typ) bias voltage of adc inputs and dac outputs. 2 vcoc o output pin for loop filter of pll circuit this pin must be connected to vss1 with one resistor and capacitor in series. 3 avdd - analog power supply pin 4 vss1 - ground pin 5 vvdd - video amp power supply pin 6 vout o composite video signal driver pin 7 vin i composite video signal input pin 8 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial csn i chip select pin (i2c pin = ?l?) 9 sda i/o control data input/output pin (i2c pin = ?h?) 10 cdtio i/o control data input/output pin (i2c pin = ?l?) this pin must be connected to the ground. (i2c pin = ?h?) cclk i control data clock pin (i2c pin = ?l?) 11 scl i control data clock pin (i2c pin = ?h?) 12 fck i/o frame clock pin 13 mcki i external master clock input pin 14 bick i/o audio serial data clock pin 15 sdti i audio serial data input pin 16 sdto o audio serial data output pin 17 pdn i power-down & reset when ?l?, the AK4636EN is in power-down mode and is held in reset. the AK4636EN must always be reset upon power-up. 18 mcko o master clock output pin 19 dvdd - digital power supply pin 20 vss2 - ground pin. 21 nc - no connection. no internal bonding. this pin must be connected to the ground. 22 spp o speaker amp positive output pin 23 svdd - speaker amp power supply pin 24 spn o speaker amp negative output pin 25 nc - no connection. no internal bonding. this pin must be connected to the ground. 26 nc - no connection. no internal bonding. this pin must be connected to the ground. 27 vss3 - ground pin 28 beep i beep signal input pin 29 aout o mono line output pin lin i line input pin for single ended input (mdif bit = ?0?, dmic bit = ?0?) micn i microphone negative input pin for differential input (mdif bit = ?1?, dmic bit = ?0?) 30 dmclk o digital microphone clock pin (dmic bit = ?1?) mic i microphone input pin for single ended input (mdif bit = ?0?,dmic bit = ?0?) micp i microphone positive input pi n for differential input (mdif bit = ?1? dmic bit = ?0?) 31 dmdat i digital microphon data input pin (dmic bit = ?1?) mpi o mic power supply pin for microphone (dmpe bit = ?0?) 32 dmp o mic power supply pin for digital microphone (dmpe bit = ?1?) note: all input pins except analog input pins (mic/micp/dmdat, lin/micn/dmclk, vin, beep pins) must not be left floating.
[ak4636] ms1012-e-01 2010/08 - 7 - handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog mic/micp, lin/micn, mpi, aout, spp, spn, vcoc, vin, vout these pins must be open. mcki, sdti these pins must be connected to vss2. cdtio when i2c pin = ?h?, these pins should be connected to vss2. digital mcko, sdto these pins must be open. absolute maximum ratings (vss=vss2=vss3=0v; note 1 ) parameter symbol min max units power supplies: analog digital speaker-amp video-amp avdd dvdd svdd vvdd ? 0.3 ? 0.3 ? 0.3 ? 0.3 4.6 4.6 4.6 4.6 v v v v input current, any pin except supplies iin - 10 ma analog input voltage ( note 2 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 3 ) vind ? 0.3 dvdd+0.3 v video-amp input voltage ( note 4 ) vinv ? 0.3 vvdd+0.3 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c maximum power dissipation ( note 5 ) pd - 450 mw note 1. all voltages with respect to ground. vss21, vss2 and vss3 must be connected to the same analog ground plane. note 2. lin/micn/dmclk, mic/micp/dmdat, beep pins note 3. pdn, i2c, csn/sda, cclk/scl, cdtio, sdti, fck, bick, mcki pins pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. note 4. vin pin note 5. ak4636ecb: when pcb wiring density is more than 200% and superficial layer wr iting density is more than 50%. AK4636EN: when pcb wiring density is more than 100%. this power is the ak4636 internal dissipation that does not include power of externally connected speakers. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ak4636] ms1012-e-01 2010/08 - 8 - recommended operating conditions (vss=vss2=vss3=0v; note 1 ) parameter symbol min typ max units power supplies ( note 6 ) analog digital speaker-amp video-amp avdd dvdd svdd vvdd 2.6 1.6 2.6 2.8 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 v v v v note 1. all voltages with respect to ground. note 6. the power up sequence between avdd, dvdd, svdd and vvdd is not critical. the internal circuit is invalid when power up the ak4636 at the pdn pin = ?h?. set the pdn pin to ?l? to reset the internal circuit after power up. to avoid an internal circuit error, the pdn pin must be ?l? upon power up, and changed to ?h? after all power supplies are supplied. the ak4636 can not be partially powered-off, all powers must be on. (power-off state is identified as when the power supplies are floating or short to ground.) when connecting the ak4636 to the i2c bus, do not turn the ak4636 off unless other external devices are off. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4636] ms1012-e-01 2010/08 - 9 - analog chracteristics (ta=25 c; avdd=dvdd=svdd = 3.3v, vvdd = 3.3v, vss1=vss2 =vss3 = 0v; fs = 8khz; lp bit = ?1? bick = 64fs; signal frequency = 1khz; 16bit data; measurement frequency = 20hz 3.4khz; ext slave mode; unless otherwise specified) parameter min typ max units mic amplifier: mic, lin pins ; mdif bit = ?0?; (single-ended input) input resistance 20 30 40 k gain (mgain3-0 bits = ?0000?) - 0 - db (mgain3-0 bits = ?0001?) 19 20 21 db (mgain3-0 bits = ?0010?) 25 26 27 db (mgain3-0 bits = ?0011?) 31 32 33 db (mgain3-0 bits = ?0100?) 9 10 11 db (mgain3-0 bits = ?0101?) 16 17 18 db (mgain3-0 bits = ?0110?) 22 23 24 db (mgain3-0 bits = ?0111?) 28 29 30 db (mgain3-0 bits = ?1000?) 2 3 4 db (mgain3-0 bits = ?1001?) 5 6 7 db mic amplifier: micp, micn pins ; mdif bit = ?1?; (full-differential input) input voltage (mgain3-0 bits = ?0001?) 0.128 0.150 0.173 vpp ( note 7 ) (mgain3-0 bits = ?0010?) 0.064 0.075 0.086 vpp (mgain3-0 bits = ?0011?) 0.032 0.038 0.044 vpp (mgain3-0 bits = ?0100?) 0.403 0.474 0.545 vpp (mgain3-0 bits = ?0101?) 0.180 0.212 0.244 vpp (mgain3-0 bits = ?0110?) 0.090 0.106 0.122 vpp (mgain3-0 bits = ?0111?) 0.045 0.053 0.061 vpp (mgain3-0 bits = ?1001?) 0.639 0.752 0.864 vpp mic power supply: mpi pin output voltage 2.1 2.3 2.5 v load resistance 2 - - k load capacitance - - 30 pf adc analog input characteristics: mic/lin ? adc, mic gain = +20db, ivol = 0db, alc1bit = ?0? resolution - - 16 bits input voltage (mic gain=20db) 0.128 0.150 0.173 vpp s/(n+d) ( ? 1dbfs) ( note 8 ) 73 83 - db d-range ( ? 60dbfs) 74 85 - db s/n 74 85 - db adc analog input characteristics: mic/lin ? adc, mic gain = 0db, ivol = 0db, alc1bit = ?0? resolution - - 16 bits input voltage (mic gain=0db) 1.28 1.50 1.73 vpp s/(n+d) ( ? 1dbfs) ( note 8 ) 73 83 - db d-range ( ? 60dbfs) 78 89 - db s/n 78 89 - db dac characteristics: resolution 16 bits mono line output characteristics: aout pin, dac aout, r l = 10k , lovl bit = ?0? output voltage lovl bit = ?0? 1.28 1.50 1.73 vpp lovl bit = ?1?( note 9 ) - 2.12 - vpp s/(n+d) (0dbfs) ( note 8 ) 74 84 - db d-range ( ? 60dbfs) 80 90 - db s/n 80 90 - db load resistance 10 - - k load capacitance - - 30 pf
[ak4636] ms1012-e-01 2010/08 - 10 - parameter min typ max units speaker-amp characteristics: dac ? spp/spn pins, alc2 bit = ?0?, r l =8 , btl, svdd=3.3v spkg1-0 bits = ?00? (-4.1dbfs) 2.54 3.17 3.80 vpp output voltage ( note 10 ) spkg1-0 bits = ?01? (-4.1dbfs) 3.20 4.00 4.80 vpp when output 150mw 40 60 - db s/(n+d) when output 400mw - 20 - db spkg1-0 bits = ?00? - -84 - dbv spkg1-0 bits = ?01? - -82 -72 dbv output noise level spkg1-0 bits = ?10? - -80 - dbv load resistance 8 - - load capacitance - - 30 pf beep input: beep pin, internal resistance mode (bpm1-0 bits = ?01?) input resistance 23 33 43 k maximum input voltage - 1.50 - vpp output voltage (input voltage=0.5vpp) beep ? spp/spn (bplvl 2-0 bits = 0h) (spkg1-0 bits = ?00?) 1.35 1.69 2.03 vpp beep ? aout (bplvl 2-0 bits = 0h) (lovl bit = ?0?) 0.40 0.50 0.60 vpp beep input: beep pin, external resistance mode (bpm1-0 bits = ?10?) input resistance= 33k maximum input voltage ( note 11 ) - 1.50 - vpp output voltage (input voltage=0.5vpp) beep ? spp/spn (bplvl 2-0 bits = 0h) (spkg1-0 bits = ?00?) - 1.69 - vpp beep ? aout (bplvl 2-0 bits = 0h) (lovl bit = ?0?) - 0.50 - vpp video signal input: maximum input voltage ( note 12 ), (gca = 0db) - 1.2 - vpp pull down current - 1 - a video signal output: output gain ( note 13 ) vin=100khz (gca = 0db) 5.3 6.0 6.7 db maximum output voltage ( note 13 ) 2.4 - - vpp output clamp voltage ( note 13 ) - 50 100 mv s/n ( note 13 ) 100kh 6mhz (gca = 0db) - 66 - db secondary harmonic distortion ( note 13 , note 14 ) vin = 3.58mhz, 0.2vpp (gca = 0db, sin wave) - ? 42 - db load resistance 140 150 - load capacitance c l 1 ( figure 3 ) c l 2 ( figure 3 ) - - - - 15 400 pf pf lpf: ( note 13 , note 14 ) frequency response response at 6.75mhz -3.0 ? 0.5 - db input=0.2vpp, sin wave (0db at 100khz) response at 27mhz - ? 40 ? 20 db frequency responce response at 6.75mhz - ? 0.5 - db input=0.2vpp, sin wave (+6db at 100khz) response at 27mhz - ? 40 - db group delay |gd3mhz ? gd6mhz| - 10 100 ns gca characteristics: step width gca = ? 1.0db ? +10.5db 0.1 0.5 0.9 db
[ak4636] ms1012-e-01 2010/08 - 11 - parameter min typ max units power supplies power up (pdn = ?h?) all circuit power-up: ( note 15 ) avdd+dvdd fs=8khz (lp bit = ?1?) ( note 17 ) - 7 - ma fs=48khz(lp bit = ?0?) ( note 17 ) - 11 17 ma svdd: speaker-amp normal opera tion (sppsn bit = ?1?, no output) - 4 12 ma vvdd ( note 16 ) - 8 12 ma power down (pdn = ?l?) ( note 18 ) avdd+dvdd+svdd+vvdd - 1 5 a note 7. the voltage difference between micp and micn pins. ac coupling capacitor should be inserted in series at each input pin. full-differential microphone input is not availa ble at mgain3-0 bits = ?1000? or ?0000?. if the input signal over those maximum voltages are input, the adc does not operate properly. note 8. when a pll reference clock is input to the fck pin in pll slave mode, s/ (n+d) of mic ? adc is 75db (typ), s/ (n+d) of dac ? aout is75db (typ). note 9. when lovl bit = ?1?, large-amplitude output may have clip noise. note 10. when spgk1-0 bits = ?01? or ?10?, large-amp litude output may have clip noise if the svdd is low. note 11. the maximum input voltage is inversely proportional to the external input resistance (rin). vout = vin rin/33k (max). the volume can not be changed by bplvl 7-0 bits in ?beep pin external input resistance mode? (bpm1-0 bits = ?10?). bplvl 7-0 bits should be fixed ?00h? to change the gain by the external resistance (rin). note 12. input voltage does not depend on vvdd voltage. note 13. measurement point is a of figure 2 . note 14. this is the value when the lowest input signal level is more than -20ire. note 15. when pll master mode (mcki=12mhz), a nd pmv = pmmp = pmadc = pmdac = pmpfil = pmspk = pmvcm = pmpll = mcko = pmao = m/s = ?1?. the mpi pin outputs 0ma. in ext mode, when pmpll= mcko= m/s= ?0? and lp= ?0?, avdd+ dvdd= 6ma (fs=8kh z, typ) or 9ma (fs=48khz, typ), when lp= ?1?, avdd+dvdd = 5ma (fs=8khz, typ). note 16. when black signal is input to the vin pin, and the vout pin has no load resistance. if the resistance is 150 , it is 12.5ma(typ). note 17. set lp bit = ?1? when sampling frequency 22.05khz, set lp bit = ?0? when > 22.05khz. note 18. all digital input pins are fixed to dvdd or vss2. vin vout clamp 75 lpf gca +6db me asu ring po int a 75 - 1db ~ +10.5db st ep 0. 5db figure 2. measurement point
[ak4636] ms1012-e-01 2010/08 - 12 - vin vout clamp 75 lpf gca +6db 75 c l 2 c l 1 r1 r2 -1db ~ +10.5db st ep 0. 5db figure 3. load capacitance c l 1 and c l 2 filter chracteristics (ta = ? 30 ~ 85 c; avdd = 2.6 3.6v, dvdd = 1.6 3.6v, svdd = 2.6 3.6v, vvdd = 2.8 3.6v; fs = 8khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 19 ) 0.16db ? 0.66db ? 1.1db ? 6.9db pb 0 - - - - 3.5 3.6 4.0 3.0 - - - khz khz khz khz stopband ( note 19 ) sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 20 ) gd - 16 - 1/fs group delay distortion gd - 0 - s dac digital filter (decimation lpf): passband ( note 19 ) 0.16db ? 0.54db ? 1.0db ? 6.7db pb 0 - - - - 3.5 3.6 4.0 3.0 - - - khz khz stopband ( note 19 ) sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 20 ) gd - 16 - 1/fs group delay distortion gd - 0 - s dac digital filter + analog filter: frequency response: 0 3.4khz fr - 1.0 - db note 19. the passband and stopband frequencies ar e proportional to fs (system sampling rate). for example, adc of pb = 3.6khz is 0.45*fs (@ ? 1.0db). a reference of frequency response is 1khz. note 20. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of a channel from the input register to the output register of the adc. for the dac, this time is from setting the 16-bit data of a channel from the input register to the output of analog signal. when there is not a phase change with the iir filter, group delay of the programmable filter (primary hpf + primary lpf + 4-band equalizer + alc) increases for 3/fs than a value above mentioned.
[ak4636] ms1012-e-01 2010/08 - 13 - dc chracteristics (ta = ? 30 ~ 85 c; avdd = 2.6 3.6v, dvdd = 1.6 3.6v, svdd = 2.6 3.6v, vvdd = 2.8 3.6v) parameter symbol min typ max units audio interface & serial p interface (cdtio, csn/sda, cclk/scl, i2c, pdn, bick, fck, sdti, mcki pins input ) high-level input voltage (dvdd 2.2v) (dvdd < 2.2v) low-level input voltage (dvdd 2.2v) (dvdd < 2.2v) vih vil 70%dvdd 80%dvdd - - - - - - - - 30%dvdd 20%dvdd v v v v audio interface & serial p interface (cdtio , sda mcko, bick, fck, sdto pins output) high-level output voltage (iout = ? 80 a) low-level output voltage (except sda pin : iout = 80 a) (sda pin, 2.0v dvdd 3.6v: iout = 3ma) (sda pin, 1.6v dvdd < 2.0v: iout = 3ma) voh vol1 vol2 vol2 dvdd ? 0.2 - - - - - - - - 0.2 0.4 20%dvdd v v v input leakage current iin - - 10 a digital mic interface (dmdat pin input ; dmic bit = ?1?) high-level input voltage low-level input voltage vih2 vil2 65%avdd - - - - 35%avdd v v digital mic interface (dmclk pin output ; dmic bit = ?1?) high-level output voltage (iout= ? 80 a) low-level output voltage (iout= 80 a) voh3 vol3 avdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a switing characteristics (ta = ? 30 ~ 85 c; avdd =2.6 3.6v, dvdd = 1.6 3.6v, svdd = 2.6 3.6v, vvdd = 2.8 3.6v; c l = 20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) ( figure 4 ) mcki input: frequency pulse width low pulse width high fclk tclkl tclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs=29.4khz, 32khz ( note 22 ) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck output: frequency pulse width high (dif1-0 bits = ?00? and fcko bit = ?1?) duty cycle (dif1-0 bits = ?00? or fcko bit = ?0?) ffck tfckh dfck 8 - - - tbck 50 48 - - khz ns % bick: period (bcko1-0 bit = ?00?) (bcko1-0 bit = ?01?) (bcko1-0 bit = ?10?) duty cycle tbck tbck tbck dbck - - - - 1/16ffck 1/32ffck 1/64ffck 50 - - - - ns ns ns %
[ak4636] ms1012-e-01 2010/08 - 14 - parameter symbol min typ max units audio interface timing dsp mode: ( figure 5 , figure 6 ) fck ? ? to bick ? ? ( note 23 ) fck ? ? to bick ? ? ( note 24 ) bick ? ? to sdto (bckp bit = ?0?) bick ? ? to sdto (bckp bit = ?1?) sdti hold time sdti setup time tdbf tdbf tbsd tbsd tsdh tsds 0.5 x tbck ? 40 0.5 x tbck ? 40 ? 70 ? 70 50 50 0.5 x tbck 0.5 x tbck - - - - 0.5 x tbck + 40 0.5 x tbck +40 70 70 - - ns ns ns ns ns ns except dsp mode: ( figure 7 ) bick ? ? to fck edge fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbfck tfsd tbsd tsdh tsds ? 40 ? 70 ? 70 50 50 - - - - - 40 70 70 - - ns ns ns ns ns pll slave mode (pll reference clock: fck pin) ( figure 8 , figure 9 ) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck ? 60 45 8 - - 48 1/ffck ? tbck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 0.4 x tbck 0.4 x tbck - - - 1/16ffck - - ns ns ns pll slave mode (pll reference clock: bick pin) ( figure 8 , figure 9 ) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck ? 60 45 8 - - 48 1/ffck ? tbck 55 khz ns % bick: period (pll3-0 bit = ?0001?) (pll3-0 bit = ?0010?) (pll3-0 bit = ?0011?) pulse width low pulse width high tbck tbck tbck tbckl tbckh - - - 0.4 x tbck 0.4 x tbck 1/16ffck 1/32ffck 1/64ffck - - - - - - - ns ns ns ns ns pll slave mode (pll reference clock: mcki pin) ( figure 10 ) mcki input: frequency pulse width low pulse width high fclk fclkl fclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs=29.4khz, 32khz ( note 22 ) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 8 tbck ? 60 45 - - - 48 1/ffck ? tbck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 0.4 x tbck 0.4 x tbck - - - 1/16ffck - - ns ns ns
[ak4636] ms1012-e-01 2010/08 - 15 - parameter symbol min typ max units audio interface timing dsp mode: ( figure 11 , figure 12 ) fck ? ? to bick ? ? ( note 23 ) fck ? ? to bick ? ? ( note 24 ) bick ? ? to fck ? ? ( note 23 ) bick ? ? to fck ? ? ( note 24 ) bick ? ? to sdto (bckp bit = ?0?) bick ? ? to sdto (bckp bit = ?1?) sdti hold time sdti setup time tfckb tfckb tbfck tbfck tbsd tbsd tsdh tsds 0.4 x tbck 0.4 x tbck 0.4 x tbck 0.4 x tbck - - 50 50 - - - - - - - - - - - - 80 80 - - ns ns ns ns ns ns ns ns except dsp mode: ( figure 14 ) fck edge to bick ? ? ( note 21 ) bick ? ? to fck edge ( note 21 ) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns ext slave mode ( figure 13 ) mcki frequency: 256fs 512fs 1024fs pulse width low pulse width high fclk fclk fclk tclkl tclkh 1.8816 3.7632 7.5264 0.4/fclk 0.4/fclk 2.048 4.096 8.192 - - 12.288 13.312 13.312 - - mhz mhz mhz ns ns fck frequency (mcki = 256fs) (mcki = 512fs) (mcki = 1024fs) duty cycle ffck ffck ffck duty 7.35 7.35 7.35 45 8 8 8 - 48 26 13 55 khz khz % bick period bick pulse width low pulse width high tbck tbckl tbckh 312.5 130 130 - - - - - - ns ns ns audio interface timing ( figure 14 ) fck edge to bick ? ? ( note 21 ) bick ? ? to fck edge ( note 21 ) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns
[ak4636] ms1012-e-01 2010/08 - 16 - parameter symbol min typ max units ext master mode ( figure 4 ) mcki frequency: 256fs 512fs 1024fs pulse width low pulse width high fclk fclk fclk tclkl tclkh 1.8816 3.7632 7.5264 0.4/fclk 0.4/fclk 2.048 4.096 8.192 - - 12.288 13.312 13.312 - - mhz mhz mhz ns ns fck frequency (mcki = 256fs) (mcki = 512fs) (mcki = 1024fs) duty cycle ffck ffck ffck dfck 7.35 7.35 7.35 - 8 8 8 50 48 26 13 - khz khz khz % bick: period (bcko1-0 bit = ?00?) (bcko1-0 bit = ?01?) (bcko1-0 bit = ?10?) duty cycle tbck tbck tbck dbck - - - - 1/16ffck 1/32ffck 1/64ffck 50 - - - - ns ns ns % audio interface timing dsp mode: ( figure 5 , figure 6 ) fck ? ? to bick ? ? ( note 23 ) fck ? ? to bick ? ? ( note 24 ) bick ? ? to sdto (bckp bit = ?0?) bick ? ? to sdto (bckp bit = ?1?) sdti hold time sdti setup time tdbf tdbf tbsd tbsd tsdh tsds 0.5 x tbck ? 40 0.5 x tbck ? 40 ? 70 ? 70 50 50 0.5 x tbck 0.5 x tbck - - - - 0.5 x tbck+40 0.5 x tbck+40 70 70 - - ns ns ns ns ns ns except dsp mode: ( figure 7 ) bick ? ? to fck edge fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbfck tfsd tbsd tsdh tsds ? 40 ? 70 ? 70 50 50 - - - - - 40 70 70 - - ns ns ns ns ns note 21. bick rising edge must not occur at the same time as fck edge. note 22. duty cycle = (the width of ?l?)/(the period of clock)*100 note 23. msbs, bckp bits = ?00? or ?11? note 24. msbs, bckp bits = ?01? or ?10?
[ak4636] ms1012-e-01 2010/08 - 17 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 26 ) tcss 50 - - ns cclk ? ? to csn edge ( note 26 ) tcsh 50 - - ns cclk ? ? to cdti (at read command) tdcd - - 70 ns csn ? ? to cdti (hi-z) (at read command) ( note 27 ) tccz - - 70 ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 28 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns reset timing pdn pulse width ( note 29 ) tpd 150 - - ns pmadc ? ? to sdto valid ( note 30 ) adrst bit = ?0? tpdv - 1059 - 1/fs adrst bit = ?1? tpdv - 291 - 1/fs digital mic interface dmclk output timing ; c l =100pf period tsck - 1/(64fs) - ns rise time tsrise - - 10 ns fall time tsfall - - 10 ns duty cycle dsck 40 50 60 % dmdat interface timing dmdat setup time tsds 50 - - ns dmdat hold time tsdh 0 - - ns note 25. i 2 c-bus is a trademark of nxp b.v. note 26. cclk rising edge must not occur at the same time as csn edge. note 27. r l = 1k ? /10% change ( pull-up to dvdd) note 28. data must be held long enough to bridge the 300ns-transition time of scl. note 29. the ak4636 can be reset by the pdn pin = ?l? note 30. this is the count of fck ? ? from the pmadc = ?1?.
[ak4636] ms1012-e-01 2010/08 - 18 - timing diagram fck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckoh tmckol 50%dvdd 1/ffck dfck dfck 50%dvdd dmck = tmckol x fmck x 100% figure 4. clock timing (pll/ext master mode) (mcko isn?t available at ext master mode) fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb msb bick 50%dvdd (bckp = "0") (bckp = "1") figure 5. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?0?)
[ak4636] ms1012-e-01 2010/08 - 19 - fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb bick 50%dvdd (bckp = "1") (bckp = "0") msb figure 6. audio interface timing (pll/ext ma ster mode & dsp mode: msbs = ?1?) fck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tbfck dbck tfsd figure 7. audio interface timing (pll/ex t master mode & except dsp mode)
[ak4636] ms1012-e-01 2010/08 - 20 - 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "0") (bckp = "1") figure 8. clock timing (pll slave mode ; pll reference clock = fck or bick pin & dsp mode; msbs = 0) 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "1") (bckp = "0") figure 9. clock timing (pll slave mode; pll reference clock = fck or bick pin & dsp mode; msbs = 1)
[ak4636] ms1012-e-01 2010/08 - 21 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl 1/fmck mcko 50%dvdd tmckoh tmckol dmck = tmckol x fmck x 100% figure 10. clock timing (pll slave mode; pll reference clock = mcki pin & except dsp mode)
[ak4636] ms1012-e-01 2010/08 - 22 - fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 11. audio interface timing (pll slave mode & dsp mode; msbs = 0) fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 12. audio interface timing (pll slave mode, dsp mode; msbs = 1)
[ak4636] ms1012-e-01 2010/08 - 23 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl figure 13. clock timing (ext slave mode) fck vih vil tbfck bick vih vil tfsd sdto 50%dvdd tfckb tbsd tsds sdti vil tsdh vih msb figure 14. audio interface timing (pll, ext slave mode & except dsp mode)
[ak4636] ms1012-e-01 2010/08 - 24 - csn vih vil tcss cclk tcds vih vil cdtio vih tcckh tcckl tcdh vil a6 a5 r/w tcck tcsh figure 15. write command input timing csn vih vil tcsh cclk vih vil cdtio vih tcsw vil d1 d0 d2 tcss figure 16. write data input timing
[ak4636] ms1012-e-01 2010/08 - 25 - csn cclk 50% dvdd cdtio vih d3 d2 d1 d0 tccz tdcd vil vih vil hi-z clock, h or l figure 17. read data output timing stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 18. i 2 c bus mode timing pmadc tpdv sdto 50%dvdd bit figure 19. power down & reset timing 1 tpd pdn vil figure 20. power down & reset timing 2
[ak4636] ms1012-e-01 2010/08 - 26 - tsck 65%avdd dmclk 35%avdd tsckl 50%avdd dsck = 100 x tsckl / tsck tsrise tsfall figure 21. dmclk clock timing dmclk 65%avdd dmdat tsds vih3 vil3 tsdh 35%avdd figure 22. audio interface timing (dclkp bit = ?1?) dmclk 65%avdd dmdat tsds vih3 vil3 tsdh 35%avdd figure 23. audio interface timing (dclkp bit = ?0?)
[ak4636] ms1012-e-01 2010/08 - 27 - operation overview system clock there are the following five clock modes to interface with external devices. ( table 1 and table 2 ) mode pmpll bit m/s bit pll3-0 bit figure pll master mode 1 1 table 4 figure 24 pll slave mode 1 (pll reference clock: mcki pin) 1 0 table 4 figure 25 pll slave mode 2 (pll reference clock: fck or bick pin) 1 0 table 4 figure 26 figure 27 ext slave mode 0 0 x figure 28 ext master mode 0 1 x figure 29 table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin fck pin 0 ?l? output pll master mode 1 256fs output master clock input for pll ( note 31 ) 16fs/32fs/64fs output 1fs output 0 ?l? output pll slave mode 1 (pll reference clock: mcki pin) 1 256fs output master clock input for pll ( note 31 ) 16fs input 1fs input pll slave mode 2 (pll reference clock: fck or bick pin) 0 ?l? output gnd 16fs/32fs/64fs input 1fs input ext slave mode 0 ?l? output 256fs/ 512fs/ 1024fs input 32fs input 1fs input ext master mode 0 ?l? output 256fs/ 512fs/ 1024fs input 32fs/64fs output 1fs output note 31. 11.2896mhz/12mhz/13.5mhz/24mhz/27mhz table 2. clock pins state in clock mode
[ak4636] ms1012-e-01 2010/08 - 28 - master mode/slave mode the m/s bit selects either master or slav e modes. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4636 is power-down mode (pdn pin = ?l?) and when exits reset state, the ak4636 is in slave mode. after exiting reset state, the ak4636 changes to master mode by bringing m/s bit = ?1?. when the ak4636 is in master mode, fck and bick pins ar e a floating state until m/s bit becomes ?1?. the fck and bick pins of the ak4636 should be pulled-down or pulled-up by about 100k resistor externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/salve mod pll mode when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4 . ether when the ak4636 is supplied stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or when the sampling frequency ch anges, the pll lock time is the same. 1) setting of pll mode r and c of vcoc pin ( note 32 ) mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 10ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 10ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 10ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 10ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 10ms others others n/a note 32. the tolerance of r is 5%, the tolerance of c is 30% table 4. setting of pll mode (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode. when pll2 bit is ?1? (pll reference clock input is the mcki pin), the sampling frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? (n/a: not available)
[ak4636] ms1012-e-01 2010/08 - 29 - when pll2 bit is ?0? (pll reference clock input is fck or bick pin), the sampling frequency is selected by fs3-2 bits. ( table 6 ) mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz fs 12khz (default) 1 0 1 x x 12khz < fs 24khz 2 1 0 x x 24khz < fs 48khz others others n/a (x: don?t care, n/a: not available) table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, after pmpll bit = ?0? ? ?1? until the pll is locked, the bick and fck pins output ?l? for a moment, and invalid frequency clock is output from the mcko pin at mcko bit = ?1?. if the mcko bit is ?0?, the mcko pin outputs ?l?. ( table 7 ) when sampling frequency is changed, bick and fck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin fck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock ?l? output invalid invalid invalid pll lock ?l? output 256fs output see table 9 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin after pmpll bit = ?0? ? ?1? or sampling frequency is changed. 256fs is output from the mcko pin when pll is locked again. adc and dac output invalid data when the pll is unlocked. for dac, the output signal should be muted by writing ?0? to daca and dacs bits in addr=02h. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?1?, m/s bit = ?0?)
[ak4636] ms1012-e-01 2010/08 - 30 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 13.5mhz, 24mhz or 27mhz) is input to the mcki pin, the mcko, bick and fck clocks are generated by an internal pll ci rcuit. the mcko output frequency is fixed to 256fs, the output is enabled by mcko bit. the bick is selected among 16fs, 32fs or 64fs, by bcko1-0 bits. ( table 9 ) in dsp mode, fck output can select duty 50% or high-output only during 1 bick cycle ( table 10 ). except dsp mode, fcko bit should be set ?0?. when bick output frequency is 16fs, the audio in terface format supports m ode 0 only (dsp mode). ak4636 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 11.2896mhz,12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 24. pll master mode mode bcko1 bcko0 bick output frequency 0 0 0 16fs (default) 1 0 1 32fs 2 1 0 64fs 3 1 1 n/a table 9. bick output frequency at master mode mode fcko fck output 0 0 duty = 50% (default) 1 1 high width = 1/fbck fbck is bick output frequency. table 10. fck output at pll master mode and dsp mode
[ak4636] ms1012-e-01 2010/08 - 31 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, bick or fck pin. the required clock to the ak4636 is generated by an internal pll circuit. input frequenc y is selected by pll3-0 bits. when bick input frequency is 16fs, the audio interface format supports mode 0 only (dsp mode). a) pll reference clock: mcki pin bick and fck inputs should be synchronized with mcko output. the phase between mcko and fck is not important. the mcko pin outputs the frequency selected by fs3-0 bits ( note 5 ) ak4636 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 11.2896mhz, 12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 25. pll slave mode 1 (pll reference clock: mcki pin)
[ak4636] ms1012-e-01 2010/08 - 32 - b) pll reference clock: bick or lrck pin the sampling frequency corresponds to a range fro m 7.35khz to 48khz by changing fs3-0 bits. ( table 6 ) ak4636 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 16fs, 32fs, 64fs figure 26 pll slave mode 2 (pll reference clock: bick pin) ak4636 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 16fs figure 27. pll slave mode 2 (pll reference clock: fck pin) the external clocks (mcki, bick and fck) should always be present whenever the adc or dac or programmable filter is in operation (pmadc bit = ?1?, pmdm bit = ?1?, pmdac bit = ?1? or pmpfil bit = ?1?). if these clocks are not provided, the ak4636 may draw excess current and it is not possible to operate properl y because utilizes dynamic refreshed logic internally. if the external clocks are not present, the adc, dac and programmable filter should be in the power-down mode (pmadc bit = pmdm bit = pmdac bit = pmpfil bit = ?0?).
[ak4636] ms1012-e-01 2010/08 - 33 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4636 becomes ext slave mode. master clock is input from the mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), fck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with fck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits. ( table 11 ) mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz fs 48khz (default) 1 x 0 1 1024fs 7.35khz fs 13khz 2 x 1 0 512fs 7.35khz fs 26khz 3 x 1 1 256fs 7.35khz fs 48khz table 11. mcki frequency at ext slave mode (p mpll bit = ?0?, m/s bit = ?0?) (x: don?t care) external slave mode does not support mode 0 (dsp mode) of audio interface format. the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequency master clock. ( table 12 , table 13 ) mcki s/n (fs = 8khz, 20khzlpf + a-weighted) dac aout 256fs 81db 512fs 89db 1024fs 89db table 12. relationship between mc ki and s/n of aout and spk-amp output noise level (svdd =3.3v,fs = 8khz, 20khzlpf + a-weighted) mcki sdti spk-amp 256fs ? 61dbv 512fs ? 75dbv 1024fs ? 83dbv table 13. relationship between mcki and output noise level of spk-amp the external clocks (mcki, bick and fck) should always be present whenever the adc or dac or programmable filter is in operation (pmadc bit = ?1?, pmdm bit = ?1?, pmdac bit = ?1? or pmpfil bit = ?1?). if these clocks are not provided, the ak4636 may draw excess current and it is not possible to operate properl y because utilizes dynamic refreshed logic internally. if the extern al clocks are not present, the adc, dac , spk and programmable filter should be in the power-down mode (pmadc bit = pmdm bit= pmdac bit = pmpfil bit = ?0?). ak4636 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 28. ext slave mode
[ak4636] ms1012-e-01 2010/08 - 34 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4636 becomes ext master mode by setting pmpll bit = ?0? and m/s bit = ?1?. master clock is input from the mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 14 ). the bick is selected among 32fs or 64fs, by bcko1-0 bits ( table 15 ). fck bit should be set to ?0?. mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz fs 48khz (default) 1 x 0 1 1024fs 7.35khz fs 13khz 2 x 1 0 512fs 7.35khz fs 26khz 3 x 1 1 256fs 7.35khz fs 48khz table 14. mcki frequency at ext master mode (p mpll bit = ?0?, m/s bit = ?1?) (x: don?t care) external master mode does not support mode 0 (dsp mode) of audio interface format. mcki should always be present whenev er the adc, dac or programmable filter is in operation (pmadc bit = ?1?, pmdm bit = ?1?, pmdac bit = ?1? or pmpfil bit = ?1?). if mcki is not provided, the ak4636 may draw excess current and it is not possible to operate properly because utilizes dynamic refresh ed logic internally. if mcki is not present, the adc, dac and programmabl e filter should be in the power-dow n mode (pmadc bit = pmdm bit = pmdac bit = pmpfil bit = ?0?). ak4636 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 32fs, 64fs mclk 256fs, 512fs or 1024fs figure 29. ext master mode mode bcko1 bcko0 bick output frequency 0 0 0 n/a 1 0 1 32fs (default) 2 1 0 64fs 3 1 1 n/a table 15. bick output frequency at master mode (n/a: not available)
[ak4636] ms1012-e-01 2010/08 - 35 - audio interface format four types of data formats are available a nd are selected by setting the dif1-0 bits. ( table 16 ) in all modes, the serial data is msb first, 2?s complement format. audio interface format s can be used in both master and slave modes. fck and bick pins are outputs in master mode, but must be inputs in slave mode. in mode 1-3, the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 16fs table 17 1 0 1 msb justified lsb justified 32fs figure 30 2 1 0 msb justified msb justified 32fs figure 31 (default) 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 32 table 16. audio interface format in mode0 (dsp mode), the audio i/f timing is changed by bckp and msbs bits. when bckp bit is ?0?, sdto data is output on a rising edge of bick, sdti data is latched on a falling edge of bick. when bckp bit is ?1?, sdto data is output on a falling edge of bick, sdti data is latched on a rising edge of bick. msb data position of sdto and sdti can be shifted for a halt period of bick by msbs bit. msbs bit bckp bit audio interface format 0 0 figure 33 (default) 0 1 figure 34 1 0 figure 35 1 1 figure 36 table 17. audio interface format in mode 0 if 16-bit data, the output of adc, is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data. fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 87 6 0 32 11 1 4 1 5 14 11 15 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 10 15 14 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 3 13 3 15 14 4 7 6 0 321 5 15 13 sdti(i) don?t care figure 30. mode 1 timing
[ak4636] ms1012-e-01 2010/08 - 36 - fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 87 6 0 32 11 1 4 1 5 14 11 15 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 13 15 14 2 1 13 0 15 sdti(i) 15 14 4 87 6 0 321 5 15 don?t care figure 31. mode 2 timing fck bick(32fs) sdto(o) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 1 15 5 13 7 7 1 43 11 1 4 2 6 0 14 11 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 14 don?t care 16 16 3 13 15 2 1 14 0 14 3 3 4 sdti(i) 15 5 13 7 1 432 6 0 14 figure 32. mode 3 timing
[ak4636] ms1012-e-01 2010/08 - 37 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 88 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 82 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 33. mode 0 timing (bckp = ?0?, msbs = ?0?) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 34. mode 0 timing (bckp = ?1?, msbs = ?0?)
[ak4636] ms1012-e-01 2010/08 - 38 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 35. mode 0 timing (bckp = ?0?, msbs = ?1?) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 5 887 1 4 3 2 6 13 10 0 2 14 14 2 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 6 0 14 14 sdti(i) bick ( 32fs ) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 36. mode 0 timing (bckp = ?1?, msbs = ?1?)
[ak4636] ms1012-e-01 2010/08 - 39 - system reset when power-up, the pdn pin should be ?l? and change to ?h ? after all powers are supplied. ?l? time of 150ns or more is needed to reset the ak4636. the adc enters an initialization cycle when the pmadc bit is changed from ?0? to ?1?. the initialization cycle time is set by adrst bit ( table 18 ). during the initialization cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ?0?. the adc output re flects the analog input signal after the in itialization cycle is complete. the same initializing cycle is occurred when using the digital mi crophone. the dac does not require an initialization cycle. (note) off-set occurs in the initial data depending on th e conditions of a microphone and cut-off frequency of hpf. when off-set becomes a problem, lengthen initialization time of adc by adrst bit = ?0? or do not use initial output data of adc. init cycle adrst bit cycle fs = 8khz fs = 16khz fs = 48khz 0 1059/fs 132.4ms 66.2ms 22.1ms 1 291/fs 36.4ms 18.2ms 6.1ms table 18 initialization cycle of adc mic/line/digital mic selector the ak4636 has an input selector. when mdif bit is ?0?, lin bit selects the mic pin or lin pin. when mdif bit is ?1?, mic/lin pins become micp/micn pins, and full-differential input is available. when dmic bit is ?1?, mic/lin pins become dmclc/ dmdat pins, and they can be connected to digital microphone. mdif bit lin bit dmic bit input circuit input pin 0 0 0 single-ended mic pin (default) 0 1 0 single-ended lin pin 1 x 0 differential micp/micn pin x x 1 digital mic dmdat/ dmclk pin table 19. input select (x: don?t care)
[ak4636] ms1012-e-01 2010/08 - 40 - mic gain amplifier the ak4636 has a gain amplifier for microphone input. these gains are selected by the mgain3-0 bit. the typical input impedance is 30k . mgain3 bit mgain2 bit mgain1 bit mgain0 bit input gain 0 0 0 0 0db 0 0 0 1 +20db (default) 0 0 1 0 +26db 0 0 1 1 +32db 0 1 0 0 +10db 0 1 0 1 +17db 0 1 1 0 +23db 0 1 1 1 +29db 1 0 0 0 +3db 1 0 0 1 +6db others n/a table 20. input gain (n/a: not available) mic power (dmpe bit = ?0?) the mpi pin supplies power for the microphone. this output voltage is 2.3v (typ) and the load resistance is minimum 2k . any capacitor must not be conn ected to the mpi pin directly. mic pin mpi pin ak4636 mic-amp 2k hpf a/d mic-power bick pin fck pin stdo pin audio i/f figure 37. mic block circuit micp pin micnpin mpi pin ak4636 mic-amp 1k 1k hpf a/d mic-power bick pin fck pin stdo pin audio i/f figure 38. mic block circuit (differential; mdif = ?1?)
[ak4636] ms1012-e-01 2010/08 - 41 - digital mic 1. connection to digital mic the ak4636 can be connected to digital mi crophone by setting dmic bit = ?1?. when dmic bit is set to ?1?, the mpi, lin and mic pins become dmp (digital microphone power supply), dmclk (digital microphone clock supply) and dmdat (digital microphone data input) pi ns respectively. by setting dmpe b it = ?1?, the dmp (digital microphone power supply) pin and can supply the power to the digital microphone (max. 2ma). when dmpe bit = ?0?, the same power supply as avdd must be provided to the digital microphone. the figure 39 and figure 40 show connection examples. the dmclk signal is output from the ak4636, and the digital microphone outputs 1bit data, which is generated by ? modulator, from dmdat. pmdml/r bits control power up/down of the digital block (decimation filter and digital filter). pmadl/pmadr bits settings do not affect the digital micr ophone power management. the dclke bit controls on/off of the clock output from the dmclk pin. when the ak4636 is powered down (pdn pin= ?l?), the dmclk and dmdat pin are floating state. pull-down resistors must be connected to the dmclk and dmdat pin externally to avoid floating state. amp ? modulator dmdat dmclk ( 64fs ) decimation filter pll mcki alc sdto programmable filter dmp vdd ak4636 avdd dmpe = ?1? 100k r hpf1 figure 39. connection example of digital mic (dmpe bit = ?1?) amp ? modulator dmdat dmclk ( 64fs ) decimation filter pll mcki alc sdto programmable filter dmp vdd ak4636 avdd dmpe = ?0? avdd 100k r hpf1 figure 40. connection example of digital mic (dmpe bit = ?0?)
[ak4636] ms1012-e-01 2010/08 - 42 - 2. interface the digital microphone outputs data when dmclk is ?h? by setting dclkp bit = ?1?, and it outputs data when dmclk is ?l? by setting dclkp bit = ?0?. the dmclk data only supports 64fs. the dmclk pin outputs is 64fs when dclke bit = ?1?. in this case, necessary clocks must be supplied to the ak4636 for adc operation. the dmclk outputs ?l? when dclke bit = ?0?. figure 41 and figure 42 show data input/output timings. when dclkp bit = ?1?, the digital microphone outputs data on the rising edge ? ? of dmclk and the ak4636 latc hes data on the falling edge ? ? of dmclk. when dclkp bit = ?0?, the digital microphone outputs data on the rising edge ? ? of dmclk and the ak4636 latches data on the falling edge ? ? of dmclk. the pdm signal is defined as 0db (full scale) when the 1 bit data density ranges 50% from 50%. dmclk(64fs) dmdat dclkp bit = ?1? valid data valid data valid data valid data figure 41. data in/output timing with digital mic (dclkp bit = ?1?) dmclk(64fs) dmdat dclkp bit = ?0? valid data valid data valid data valid data figure 42. data in/output timing with digital mic (dclkp bit = ?0?)
[ak4636] ms1012-e-01 2010/08 - 43 - digital block the digital block consists of block diagram as shown in figure 43 . the ak4636 can choose signal process path on a recording path or on a playback path by setting adcpf bit, pfdac bit and pfsdo bit. ( figure 43 ~ figure 46 , table 21 ) dac 1st orde r hpf1 adc alc (volume) datt smute sdti a dcpf bit ?1? ?0? 4 band eq 1st order hpf2 pfdac bit ?1? ? 0? pfsdo bit ?0? ? 1? sdto hpf bit eq2-5 bits pmpfil bit pmdac bit pmadc bit 1st order lpf lp f bit eq eq1 bit (1) adc: include a digital filter (lpf) for adc as shown in ?filter chracteristics?. (2) dac: include a digital filter (lpf) for dac as shown in ?filter chracteristics?. (3) hpf1/2: high pass filter. applicable to use as wind-noise reduction filter. (see ?programmable filter?.) (4) lpf: low pass filter (see ?digital programmable filter?.) (5) 4-band eq: applicable to use as an equalizer or notch filter. (see ?digital programmable filter?.) (6) alc: input digital volume with alc function. (see ?input digital volume? and ?alc?.) (7) eq: applicable to use as an equalizer or no tch filter. (see ?digital programmable filter?.) (8) datt: 4-step digital volume for playback path. (see ?digital volume 2?) (9) smute: soft mute. (see ?soft mute?.) figure 43. digital block path select
[ak4636] ms1012-e-01 2010/08 - 44 - mode adcpf bit pfdac bit pfsdo bit figure recording mode 1 0 1 figure 44 (default) playback mode 0 1 0 figure 45 loop back mode 1 1 1 figure 46 table 21 recording reproduction mode dac 2nd order hpf adc 4 band eq alc (volume) datt smute 1st order lpf eq figure 44. path at recording mode (default) dac 1st order hpf adc datt smute alc (volume) 4 band eq 1st order hpf 1st order lpf eq figure 45. path at playback mode dac 2nd order hpf adc 4 band eq alc (volume) datt smute 1st order lpf eq figure 46. path at recording & playback mode
[ak4636] ms1012-e-01 2010/08 - 45 - h(z) = a 1 ? z ? 1 1 ? bz ? 1 digital programmable filter circuit the ak4636 has 2 steps of 1 st order hpf, 1 st order lpf and 5-band equalizer built-in on recording/playback paths. (1) high pass filter (hpf1/2) normally, this hpf is used as a wind-noise reduction filter. this is composed with 2 steps of 1st order hpf. the coefficient of both hpf is the same and set by f1a13-0 bits and f1b13-0 bits. hpf bit controls on/off of the hpf2. when the hpf2 is off, the audio data passes this block by 0db gain. the coefficient should be set when pmadc = pmpfil bits = ?0?. fs : sampling frequency fc : cut-off frequency register setting ( note 33 ) hpf: f1a[13:0] bits = a, f1b[13:0] bits = b (msb = f1a13, f1b13; lsb = f1a0, f1b0) a = 1 1 + tan ( fc/fs) b = 1 ? tan ( fc/fs) 1 + tan ( fc/fs) , transfer function the cut-off frequency should be set as below. fc/fs 0.0001 (fc min = 1.6hz at fs=16khz) (2) low pass filter(lpf) this is composed with 1st order lpf. f2a13-0 bits and f2b 13-0 bits set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coefficient should be set when lpf bit = ?0? or pmpfil bits = ?0?. fs : sampling frequency fc : cut-off frequency register setting ( note 33 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f1b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1 the cut-off frequency should be set as below. fc/fs ? 0.05 (fc min = 2205hz at fs=44.1khz)
[ak4636] ms1012-e-01 2010/08 - 46 - (3) 4-band equalizer and equalizer after alc this block can be used as equalizer or notch filter. on/off 5-band equalizer (eq2, eq3, eq4 and eq5) can be controlled independently by eq2, eq3, eq4 and eq5 bits. the equalizer after alc (eq1) can be on/off by eq1 bit. when equalizer is off, the audio data passes this block by 0db gain. e1a15-0, e1b15-0 and e1c15-0 bits set the coefficient of eq1. e2a15-0, e2b15-0 and e2c15-0 bits set the coefficient of eq2. e3a15-0, e3b15-0 and e3c15-0 bits set the coefficient of eq3. e4a15-0, e4b15-0 and e4c 15-0 bits set the coefficient of eq4. e5a15-0, e5b15-0 and e5c15-0 bits set the coefficient of eq5. each eq coeffi cient setting should be made when the corresponding eq bit is ?0? or pmpfil bit ?0?. fs : the sampling frequency fo 1 ~ fo 5 : the center frequency fb 1 ~ fb 5 : the band width where the gain is 3db different from center frequency k 1 ~ k 5 : the gain ( -1 k n < ?3 ) register setting ( note 33 ) eq1: e1a[15:0] bits = a 1 , e1b[15:0] bits = b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits = a 2 , e2b[15:0] bits = b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits = a 3 , e3b[15:0] bits = b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits = a 4 , e4b[15:0] bits = b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits = a 5 , e5b[15:0] bits = b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0 , e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 h(z) = ( 1 + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) ) x {1 + h 1 (z)} (n = 1, 2, 3, 4, 5) the center frequency should be set as below fo n / fs < 0.497 when gain of k is set to ? ? 1?, the equalizer becomes notch filter. the central frequency of a real notch filter deviates from the above calculation, if the central frequency of each band is n ear. the control soft that is attached to the evaluation board has a function that revises a gap of freque ncy, and calculates the coefficient. wh en the central frequency of each band is near, revise the central frequency and confirm the frequency response. note 33. [translation the filter coefficient calculate d by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit.
[ak4636] ms1012-e-01 2010/08 - 47 - input digital volume (manual mode) when adcpf bit = ?1? and alc1 bit = ?0?, the alc block becomes an input digital volume (manual mode). the digital volume?s gain is set by ivol7-0 bits as shown in table 22 . the ivol value is changed at zero cross or zero cross time out. the zero crossing timeout period is set by ztm1-0 bits. ivol7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 22. input digital volume setting when writing to the ivol7-0 bits conti nually, the control register should be written in an interval more than zero crossing timeout. if not, a zero crossing c ounter is reset at each time and the vol ume will not be changed. however, it could be ignored when writing the same regi ster value as the last time. at this time, zero crossing counter is not reset, so it can be written in an interval less than zero crossing timeout.
[ak4636] ms1012-e-01 2010/08 - 48 - output digital volume (manual mode) when adcpf bit = ?0? and alc2 bit = ?0?, the alc block becomes an output digital volume (manual mode). the digital volume?s gain is set by ovol7-0 bits as shown in table 23 . the ovol7-0 bits value are reflected to this output volume at zero cross or zero cross time out. the zero crossing timeout period is set by ztm1-0 bits. ovol7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 23 output digital volume setting when writing to the ovol7-0 bits continually, the control re gister should be written by an interval more than zero crossing timeout. if not, a zero crossing count er is reset at each time and the volum e will not be changed. however, it could be ignored when writing a same regist er value as the last time. at this time, zero crossing c ounter is not reset, so it can be written by an interval less than zero crossing timeout. output digital volume2 ak4636 has 4 steps output volume in additi on to the volume setting by ovol7-0 bits . this volume is set by datt1-0 bits as shown in table 24 . datt1-0bits gain(0db) step 0h 0.0 (default) 1h -6.0 2h -12.0 6.0db 3h -18.1 table 24. output digital volume2 setting
[ak4636] ms1012-e-01 2010/08 - 49 - output digital volume3 the ak4636 has a digital output volume (dvol) with 256 levels in linear steps ( table 24 ). the volume can be set by the dvl7-0 and dvr7-0 bits. the volume is included in front of a dac block. the input data of dac is changed from +0.35 to ?47.78db or mute. the volume calculating formula is shown in table 26 . dvol7-0 bits att_data gain(0db) ffh 255 +0.35 feh 254 +0.31 : : : f5h 245 0 (default) : : : 02h 2 -41.76 01h 1 -47.78 00h - mute table 25. output digital volume3 setting dvol7-0 bits gain (db) ffh : 0.35 + 20 log 10 (att_data / 255) 01h 00h mute table 26. output digital volume3 formula
[ak4636] ms1012-e-01 2010/08 - 50 - alc operation the alc (automatic level control) is operated by alc bl ock. when adcpf bit = ?1?, alc operation is enable at recording path. when adcpf bit = ?0?, alc operation is enable at playback path. on/off switching of alc operation is controlled by alc1 bit for recording and alc2 bit for playback. 1. alc limiter operation during the alc limiter operation, if the output data exceeds the alc limiter detection level ( table 27 ), the volume value is automatically attenuated by the amount defined in lmat1-0 bits ( table 28 ). when zelmn bit = ?0? (zero cross detec tion valid), the ivl and vol value is changed by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both alc limiter and recovery operation ( table 29 ). when alc output level exceeds full-scale at lfst bit = ?1?, vol value is immediately (period: 1/fs) changed in 1 st ep. when alc output level is less than full-scale, vol value is changed at the individual zero crossing point of each channels or at the zero crossing timeout. when zelmn bit = ?1? (zero cross detection invalid), vol va lue is immediately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. after completing the attenuate operation, unless alc bit is ch anged to ?0?, the operation repeats when the input signal level exceeds the alc limiter detection level. lmth1 lmth0 alc limiter detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs (default) 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 27. alc limiter detection level / recovery waiting counter reset level alc1 limiter att step lmat1 lmat0 alc1 output lmth alc1 output fs alc1 output fs + 6db alc1 output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 28. alc limiter att step setting zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 29. alc zero crossing timeout period setting
[ak4636] ms1012-e-01 2010/08 - 51 - 2. alc recovery operation the alc recovery operation waits for the wtm2-0 bits ( table 30 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 27 ) during the wait time, the alc recovery operation is executed. the vol value is automatically incremented by rgain1-0 bits ( table 31 ) up to the set reference level ( table 32 , table 33 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 29 ). the alc recovery operation is executed in a period set by wtm2-0 bits. for example, when the current vol value is 30h and rgain1-0 bits are set to ?01?(2 steps), vol is changed to 32h by the auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the vol value exceeds the reference level (iref7-0 or oref 5-0), the vol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when larg e noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast r ecovery operation. the speed of first recovery operation is set by rfst1-0 bits ( table 34 ). alc recovery operation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 30. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 0.375db (default) 0 1 2 0.750db 1 0 3 1.125db 1 1 4 1.500db table 31. alc recovery gain step
[ak4636] ms1012-e-01 2010/08 - 52 - iref7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 (default) : : 92h +0.375 91h 0.0 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 32. reference level at alc recovery operation for recoding oref5-0bits gain(0db) step 3ch +36.0 3bh +34.5 3ah +33.0 : : 28h +6.0 (default) : : 25h +1.5 24h 0.0 23h -1.5 : : 1.5db 2h -51.0 1h -52.5 0h -54.0 table 33. reference level at alc recovery operation for playback rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 34. first recovery speed setting (n/a: not available)
[ak4636] ms1012-e-01 2010/08 - 53 - 3. the volume at the alc operation the current volume value at the alc operati on is reflected in vol7-0 bits. it is en able to check the current volume value by reading the register value of vol7-0 bits. vol7-0bits gain(0db) f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 : : 92h +0.375 91h 0.0 90h ? 0.375 : : 2h ? 53.625 1h ? 54.0 0h mute table 35. value of vol7-0 bits 4. example of the alc operation for recording table 36 shows the examples of the alc setting for a microphone recording. fs=8khz fs=16khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelm limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms wtm2-0 recovery waiting period *wtm1-0 bits should be more than or equal to ztm1-0 bits 000 16ms 001 16ms iref7-0 maximum gain at recovery operation c5h 19.5db c5h 19.5db ivol7-0 gain of ivol c5h 19.5db c5h 19.5db lmat1-0 limiter att step 00 1step 00 1step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step alc1 alc enable 1 enable 1 enable frsl1-0 speed of fast recovery 00 4 times 00 4times table 36. example of the alc setting (recording)
[ak4636] ms1012-e-01 2010/08 - 54 - 5. example of alc for playback operation table 37 shows the example of the alc setting for playback. fs=8khz fs=16khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelm limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms wtm2-0 recovery waiting period *wtm1-0 bits should be more than or equal to ztm1-0 bits 000 16ms 001 16ms oref5-0 maximum gain at rec overy operation 28 +6db 28 +6db ovol7-0 gain of ivol 91 0db 91 0db lfst fast limiter operation 1 on 1 on lmat1-0 limiter att step 00 1step 00 1step rgain1-0 recovery gain step 00 1 step 00 1 step alc2 alc enable 1 enable 1 enable frsl1-0 speed of fast recovery 00 4 times 00 4 times table 37. examples of the alc setting (playback)
[ak4636] ms1012-e-01 2010/08 - 55 - 6. noise suppression the noise suppression is enabled when nsce bit (noise s uppression enable bit) = ?1? during alc operation (alc1 bit = ?1?). this function attenuates output signal level automatically when minute amount of the signal is input. nsce bit: noise suppression enable 0: disable (default) 1: enable (1) noise level suppressing operation the output signal ( note 34 ) is suppressed when the input peak level is lower than ?noise suppression threshold low level? set by nsthl3-0 bits ( table 38 ) during the waiting time set by wtm2-0 bits ( table 30 ). vol value is changed by this noise s uppressing operation only at the individual zero crossing points of lch and rch or at the zero crossing timeout. noise level suppressing operation has common zero cross timeout period to alc recovery operation which is set by ztm1-0 bits. ( table 29 ) this operation sets the volume automatically to the reference level ( table 42 ) with zero cross detection in the period which is set by ztm1-0 bits ( table 29 ). it is executed in the cycle of wtm2-0 bits settings. note 34. when the input signal volume is smaller than the value set by nsref7-0 bits, normal alc recovery operation is executed. nsthl3 nsthl2 nsthl1 nsthl0 noise suppression threshold low level step 0 0 0 0 ? 81db (default) 0 0 0 1 ? 78db 0 0 1 0 ? 75db 0 0 1 1 ? 72db 0 1 0 0 ? 69db 0 1 0 1 ? 66db 0 1 1 0 ? 63db 0 1 1 1 ? 60db 1 0 0 0 ? 57db 1 0 0 1 ? 54db 1 0 1 0 ? 51db 3db table 38. noise suppression threshold low level natt1 bit natt0 bit att step 0 0 1/4 ( note 35 ) 0 1 1/2 ( note 36 ) (default) 1 0 1 1 1 2 table 39. noise att settings note 35. 1step attenuated in 4 x ?wtm cycles?. note 36. 1step attenuated in 2 x ?wtm cycles?.
[ak4636] ms1012-e-01 2010/08 - 56 - zero cross timeout period ztm1 bit ztm0 bit 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 29. alc zero cross timeout period settings (2) noise level hold during the waiting time set by wtm2-0 bits ( table 3 ), vol values are kept when the input signal peak level is in between the set value of nsthh1-0 ( note 37 ) and noise suppression threshold low level (noise suppression high level >input signal level noise suppression threshold low level) theref ore the output signal level does not change. nsthh1 bit nsthh0 bit noise suppression high level ( note 37 ) 0 0 nsthl3-0bits + 3db 0 1 nsthl3-0bits + 6db (default) 1 0 nsthl3-0bits + 9db 1 1 nsthl3-0bits + 12db note 37. noise suppression threshold low level (nsthl3- 0 bits) + gain (nsthh1-0 bits) = noise suppression high level table 40. noise suppre ssion high level settings (3) noise suppression normal alc operation during noise suppressing opera tion, if the input signal level exceeds no ise suppression high level, the operation switches to normal alc operation from noise suppressing or noise level hold operation. in this case, recovery speed is faster than the normal recovery. ( table 41 ) when the internal volume level is lower than noise suppre ssing operation reference level (set by nsref7-0 bits), the recovery speed to alc operation from noise suppressing operation is the same as normal alc recovery speed. nsgain1 bit nsgain0 bit recovery speed 0 0 8 step 0 1 12 step (default) 1 0 16 step 1 1 28 step table 41. fast recovery speed setting from noise suppression to alc operation
[ak4636] ms1012-e-01 2010/08 - 57 - nsref7-0 bits gain[db] step f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 : : 92h +0.375 91h 0.0 (default) 90h ? 0.375 : : 0.375db 2h ? 53.625 1h ? 54.0 0h mute table 42. reference value setting when noise suppression is on
[ak4636] ms1012-e-01 2010/08 - 58 - 7. example of alc operation the following registers must not be changed during the alc operation. these bits should be changed, after the alc operation is finished by alc1 bit = alc2 bit = ?0? or pmpfil bit = ?0?. when alc is restarted, after alc1 bit and alc2 bit set to ?0? or pmpfil bit sets to ?0?, the waiting time of zero crossing timeout is not needed. lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1-0, iref7-0/oref5-0, zelm, rfst1-0, lfst, nsce, nsthl3-0, nst hh1-0, nsgain1-0, nsref7-0 bits manual mode wr (ztm1-0, wtm2-0) wr (iref7-0/oref5-0) wr (ivol7-0/ovol7-0) wr (lfst,lmat1-0, rgain0, zelmn, lmth0) wr ( alc1= ?1? ) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 lfst = 1 maximum gain = +19.5db limiter detection level = ? 4.1dbfs alc1 bit = ?1? (1) addr=06h, data=00h (2) addr=08h, data=c5h (5) addr=07h, data=a1h (3) addr=09h, data=c5h alc operation wr (rgain1, lmth1,rfst1-0) (4) addr=0bh, data=28h *2 *1 note. wr: write *1: the value of volume at starting should be the same or smaller than ref?s. *2: when setting alc1 bit or alc2 bit to ?0?, the operation is shifted to manual mode after passing the zero crossing time set by ztm1-0 bits. figure 47. registers set-up sequence at the alc operation
[ak4636] ms1012-e-01 2010/08 - 59 - softmute soft mute operation is performed in the digital input domain. when the smute bit changes to ?1?, the input signal is attenuated by ? (?0?) in 245/fs cycles (31msec@fs=8khz, dvol bits = f5h). when the smute bit is returned to ?0?, the mute is cancelled and the input attenuation gradually cha nges to 0db in 245/fs cycles (31msec@fs=8khz, dvol bits = f5h). if the soft mute is cancelled within the 245/fs cycles (31msec@fs=8khz, dvol bits = f5h), the attenuation is discontinued and returned to 0db. the soft mute for play back operation is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation 245/fs 0db - 245/fs gd gd (1) (2) (3) a nalog output figure 48. soft mute function (1) the input signal is attenuated by ? (?0?) in 245/fs cycles (31msec@fs=8khz, dvol bits = f5h). (2) analog output corresponding to digital input has group delay (gd). (3) if the soft mute is cancelled within the 245/fs cycles (31msec@fs=8khz, dvol bits = f5h), the attenuation is discounted and returned to 0db within the same cycle.
[ak4636] ms1012-e-01 2010/08 - 60 - beep input and generating circuit the ak4636 has the beep pin (external signal i nput pin) and beep generating circuit. beep mode can be set by bpm1-0 bits. bpm1 bit bpm0 bit beep mode 0 0 disable (default) 0 1 beep pin (internal resisitance mode) 1 0 beep pin (external resisitance mode) 1 1 beep generator mode table 43. beep mode settings 1. beep input pin (bpm1-0 bits =?01? or ?10?) when bmp1-0 bits = ?01? or ?10?, the input signal to b eep pin is output from the speak er amplifier by setting beeps bits to ?1?, and it is output from mono line out amplifier by setting beepa bit to ?1?. bpm1-0 bits = ?10? r i can control the beep signal gain which is in invert proportional to r i resister value ( figure 49 ). the gain setting can not be made by bplvl2-0 bits. bpm1-0 bits = ?01? the beep signal gain is controlled by bplvl2-0 bits ( table 46 ). r i is not necessary. be ep - + 33k 30% ri ci figure 49. block diagram of beep pin (bpm1-0 bits =?10?) spkg1-0 bits beep spp/spn gain 00 +10.6db 01 +12.6db 10 +14.6db 11 +16.6db table 44.beep spk output gain lovl bit beep aout gain 0 0db 1 +3db table 45.beep aout output gain
[ak4636] ms1012-e-01 2010/08 - 61 - bplvl2 bplvl1 bplvl0 beep gain aout (lovl =?0?) spk (spkg1-0 bits = ?00?) 0 0 0 0db 1.5vpp 5.08vpp (default) 0 0 1 ? 3db 1.06vpp 3.60vpp 0 1 0 ? 6db 0.75vpp 2.55vpp 0 1 1 ? 12db 0.38vpp 1.28vpp 1 0 0 ? 18db 0.19vpp 0.64vpp 1 0 1 ? 23db 0.10vpp 0.36vpp 1 1 0 ? 29db 0.05vpp 0.18vpp 1 1 1 ? 34db 0.03vpp 0.10vpp table 46. beep output gain setting when bpm 1-0 bits = ?01? (beep input =1.5vpp) 2. beep signal generating circuit the ak4636 integrates a bepp signal generating circuit. when bpm 1-0 bits = ?11?, the speaker amplifier outputs beep signal by setting beeps bit = ?1?, and the mono line out amplifier outputs beep si gnal by setting beepa bit = ?1?. after outputting the signal during the time set by bpon7-0 bits, the ak4636 stops the output signal during the time set by bpoff7-0 bits ( figure 50 ). the repeat count is set by bptm6-0 bit, and the output level is set by bplvl2-0 bits. when bpcnt bit is ?0?, if bpout bit is wr itten ?1?, the ak4636 outputs the beep for the times of repeat count. when the output is finished, bpout bit is set to ?0? automatically. when bpcnt bit is set to ?1?, it outputs the beep in succession regardless of repeat count, on-time and off-time. the output frequency is set by bpfr1-0 bits. < setting parameter > 1) output frequency ( table 47 ~ table 49 ) 2) on time ( table 50 ) 3) off time ( table 51 ) 4) repeat count ( table 52 ) 5) output level ( table 53 ) * bpfr1-0, bpon7-0, bpoff7-0, bptm6-0 and bplvl3-0 bits should be set when bpout =bpcnt = ?0?. * bpcnt bit is given priority in bpout bit. when bpout bit be set to ?1?, if bpcnt bit is set to ?0?, bpout bit is set to ?0? forcibly. * when stopping the beep outputs by changing bpcnt bit to ?0? from ?1?, writing to bpout bit and bpcnt bit are inhibited for 10ms. beep output on time off time repeat count figure 50. beep signal output
[ak4636] ms1012-e-01 2010/08 - 62 - output frequency of beep generator [hz] bpfr1-0 bit fs = 48khz system ( note 38 ) fs = 44.1khz system ( note 39 ) 00 4000 4009 (default) 01 2000 2005 10 1000 1002 11 n/a note 38. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 39. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 47. beep signal frequency (pll master/slave m ode: reference clock: mcki) (n/a: not available) output frequency of beep generator [hz] bpfr1-0 bit fs3-2 bits = ?00? fs3-2 bits = ?01? fs3-2 bits = ?10? 00 fs/2.75 fs/5.5 fs/11 (default) 01 fs/5.5 fs/11 fs/22 10 fs/11 fs/22 fs/44 11 n/a table 48. beep signal frequency ( pll slave mode: re ference clock : fck/bick) (n/a: not available) output frequency of beep generator [hz] bpfr1-0 bit fs1-0 bits = ?00? fs1-0 bits = ? 01? fs1-0 bits = ?10? fs1-0 bits = ?11? 00 fs/11 fs/2.75 fs/55 fs/11 (default) 01 fs/22 fs/5.5 fs/11 fs/22 10 fs/44 fs/11 fs/22 fs/44 11 n/a table 49. beep signal frequency (ext slave/master mode) (n/a: not available) on time of beep generator [msec] step [msec] bpon7-0 bit fs = 48khz system ( note 38 ) fs = 44.1khz system ( note 39 ) fs = 48khz system ( note 38 ) fs = 44.1khz system ( note 39 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 4h 40.0 39.9 : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 38. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 39. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 50. beep output on-time (pll master/slave mode reference clock: mcki)
[ak4636] ms1012-e-01 2010/08 - 63 - off time of beep generator [msec] step [msec] bpoff7-0 bit fs = 48khz system ( note 38 ) fs = 44.1khz system ( note 39 ) fs = 48khz system ( note 38 ) fs = 44.1khz system ( note 39 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 4h 40.0 39.9 : : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 38. sampling frequency is 8khz, 16khz, 32khz or 48khz. note 39. sampling frequency is 11.025khz, 22.05khz or 44.1khz. table 51. beep output off-time (pll master/slave mode reference clock: mcki) bptm6-0 bit repeat count 0h 1 (default) 1h 2 2h 3 3h 4 : : 7dh 126 7eh 127 7fh 128 table 52. beep output repeat count bplvl2-0 bits beep output level step 0h 0db (default) 1h ? 3db 2h ? 6db 3db 3h ? 12db 4h ? 18db 6db 5h ? 23db 5db 6h ? 29db 6db 7h ? 34db 5db note 40. beep output amplitude in 0db setting is 1.5vpp (lovl bit = ?0?) from aout, and 5.08vpp @8 ? (spkg1-0 bits = ?00?) fro m the speaker amplifier. table 53. beep output level
[ak4636] ms1012-e-01 2010/08 - 64 - mono line output (aout pin) a signal of dac is output from th e aout pin. when the daca bit is ?0?, this output is off. when the lovl bit is ?1?, this gain changes to +3db (large amplitude outputs may clip). the load resistance is 10k (min). when pmao bit is ?0? and aops bit is ?0?, the mono line output enters power-down state and it is pulled down by 100 (typ). if pmao bit is controlled when aops bit = ?1?, pop noise will be reduced at power-up and down. then, this line should be pulled down by 20k of resister after c-coupling shown in figure 51 . this rising and falling time is max 300 ms at c = 1.0 f. when pmao bit is ?1? and aops bit is ?0?, the mono line output enters power-up state. dac aout input level lovl bit gain out 0 0db 1.5vpp (default) 0dbfs 1 +3db 2.12vpp table 54. mono line ou tput volume setting aout 1 f 220 20k figure 51. aout external circuit when using pop reduction function aout control sequence in case of using pop reduction circuit p m a o bit a ops bit a out pin (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 52. mono line output control sequence when using pop reduction function (1) set aops bit = ?1?. mono line output enters the power-save mode. (2) set pmao bit = ?1?. mono line output exits the power-down mode. aout pin rises up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f. (3) set aops bit = ?0? after aout pin rises up. mono line output exits the power-save mode. mono line output is enabled. (4) set aops bit = ?1?. mono line output enters power-save mode. (5) set pmao bit = ?1?. mono line output enters power-down mode. aout pin falls down to vss1. fall time is 200ms (max 300ms) at c=1 f. (6) set aops bit = ?0? after aout pin falls down. mono line output exits the power-save mode.
[ak4636] ms1012-e-01 2010/08 - 65 - speaker output ak4636 has a mono class-d speaker-amp. power supply for speaker-amp can be set from 2.6v up to 3.6v. the output signal from dac is input to the speaker-amp. this speaker-amp is a mono output controlled by btl and the gain of speaker-amp is set by spkg1-0 bits. the output voltage is depend on spkg1-0 bits. dac spk-amp output level spkg1-0 bits gain out (r=8 ? ) 00 10.6db 3.17vpp 157mw (default) 01 12.6db 4.00vpp 250mw 10 14.6db 5.03vpp 395mw -4.1dbfs 0.94vpp 11 n/a n/a n/a note 41. the setting of spkg1-0 bits = ?01? is recommended when 8 dynamic speaker is connected. the spk-amp power is 250mw at 8 load resistance and 4.0vpp output level. table 55. spk- amp gain < speaker-amp control sequence > speaker-amp is powered-up/down by pmspk bit. when pmspk bit is ?0?, both spp and spn pins are in hi-z state. when pmspk bit is ?1? and sppsn bit is ?0?, the speaker-amp enters power-sav e mode. in this mode, the spp pin is placed in hi-z state and the spn pin outputs svdd/2 voltage. when the pmspk bit is ?1? after the pdn pin is changed from ?l? to ?h?, the spp and spn pins are powered-up in power-save-mode. in this mode, the spp pin is placed in a hi-z state and the spn pin goes to svdd/2 voltage and pop noise can be reduced. when the ak4646 is powered-down, pop noise can be also reduced by first entering power-save-mode. pmspk bit sppsn bit spp pin spn pin svdd/2 svdd/2 hi-z hi-z hi-z hi-z >t1(note) >0 (note) sppsn bit should be set to ?1? at more than 1ms after pmspk bit is set to ?1?. when beep input amp and speaker amp are powered-up at the same time, sppsn b it should be set to ?1? after beep input become stable. when the resistance and capacitance of beep pin are r=33k and c=0.1 f, 16.5ms(=5 ) is required for beep input to become stable. figure 53. power-up/power-down timing for speaker-amp
[ak4636] ms1012-e-01 2010/08 - 66 - video block the ak4636 has a video-amp with driv ability for a load resistance of 150 . it has a composite input and output. a low pass filter (lpf) and gain control amp (gca) are in tegrated and dc output is supported as shown in figure 54 . the output clamp voltage is 50 mv(typ) at dc output. the gain control and the step are shown in table 56. the gain can be set by vgca4-0 bits. pmv bit controls the power up and down of the video block. the vout pin outputs 0v at pmv bit = ?0?. when no data is input to the vin pin, pmv bit must be ?0?. vin v out clamp 75 lpf gca +6db -1db ~ +10.5db step 0.5db 0.1uf ( 50% ) figure 54. video block vgca4-0 bits gain(db) step 17h +10.5db 16h +10.0db 15h +9.5db : : 0.5db 04h +1.0db 03h +0.5db 02h 0.0db (default) 01h ? 0.5db 00h ? 1.0db table 56. recommended value of video input resistance video input the video input signals must be c coupled by a 0.1 f (50%) capacitor. the output impedance of video input signal source should be 30 ? ~390 ? (5%).
[ak4636] ms1012-e-01 2010/08 - 67 - serial control interface (1) 3-wire serial control mode internal registers may be written and r ead by the 3-wire p interface pins (c sn, cclk and cdtio). the data on this interface consists of read/write, register address (msb first, 7bits) a nd control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is cloc ked out on the falling edge. data writing is valid on the rising edge of the 16th cclk after the falling edge of csn. in r eading operation, the cdtio pin changes to output mode at the falling edge of 8th cclk and outputs d7-d0. the output fini shes on the rising edge of csn. however this reading function is available only at read bit = ?1?. when read bit = ?0?, the cdtio pin stays as hi-z even after the falling edge of 8th cclk. the cdtio pin is placed in a hi-z st ate except outputting data at r ead operation mode. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at the pdn pin = ?l?. note 42. a read operation is available at 00h ~ 11h, 1ch ~ 24h and 27h~30h addresses. when reading the address 12h ~ 1bh, 25h ~ 26h and 31h ~ 4fh, the register values are invalid. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdtio a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write, ?0?: read) a6-a0: register address d7-d0: control data clock, ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? ?h? or ?l? figure 55. serial control i/f timing
[ak4636] ms1012-e-01 2010/08 - 68 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4636 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at sda and scl pins should be connected to (dvdd+0.3)v or less voltage. (2)-1. write operations figure 56 shows the data transfer sequence for i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 62 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010010? ( figure 57 ). if the slave address matches that of the ak4636, the ak4636 generates an acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 63 ). a r/w bit value of ?1? indicates that the r ead operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4636. the format is msb first, and those most significant 1-bits are fixed to zeros ( figure 58 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 59 ). the ak4636 generates an acknowledge after each by te is received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 62 ). the ak4636 can perform more than one by te write operation per sequence. after receipt of the third byte the ak4636 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after r eceiving each data packet the inte rnal 6-bit address counter is incremented by one, and the next data is automatically taken into the next addr ess. if the address exceeds 4fh prior to generating stop condition, the address c ounter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 64 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 56. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 0 r/w figure 57. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 58. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 59. byte structure after the second byte
[ak4636] ms1012-e-01 2010/08 - 69 - (2)-2. read operations set the r/w bit = ?1? for read operation of the ak4636. after a transmission of data, if the master generates an acknowledge instead of terminating a write cycle, the internal 7-bit address counter of the ak4636 is incremented by one, and the next data is automatically taken into the next addre ss so that the data can be read from the ak4636. if the address exceeds 4fh prior to generating a stop condition, the address c ounter will ?roll over? to 00h and the data of 00h will be read out. note 42. a read operation is available at 00h ~ 11h, 1ch ~ 24h and 27h~30h addresses. when reading the address 12h ~ 1bh, 25h ~ 26h and 31h ~ 4fh, the register values are invalid. the ak4636 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4636 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit ?1?, the ak4636 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master doe s not generate an acknowledge but inst ead generates a stop condition, the ak4636 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 60. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave address with the r/w bit set to ?1?. the ak4636 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but instead generates a stop condition, the ak4636 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 61. random address read
[ak4636] ms1012-e-01 2010/08 - 70 - scl sda stop condition start condition s p figure 62. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 63. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 64. bit transfer on the i 2 c-bus
[ak4636] ms1012-e-01 2010/08 - 71 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm pmbp pmspk pmao pmdac 0 pmadc 01h power management 2 pm v 0 0 0 m/s 0 mcko pmpll 02h signal select 1 sppsn beeps dacs daca mgain3 pmmp mgain2 mgain0 03h signal select 2 pfsdo aops mgain1 spkg1 spkg0 beepa pfdac adcpf 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 05h mode control 2 adrst fcko fs3 msbs bckp fs2 fs1 fs0 06h timer select 0 wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 09h input digital volume control ivol7 ivol6 ivol5 ivol4 ivol3 ivol2 ivol1 ivol0 0ah output digital volume control ovol7 ovol6 ovol5 ovol4 ovol3 ovol2 ovol1 ovol0 0bh alc mode control 3 rgain 1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 0ch video mode control vdc1 vdc2 0 vgca4 vgca3 vgca2 vgca1 vgca0 0dh alc level vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 0eh signal select 3 datt1 datt0 smute mdif 0 0 0 read 0fh digital volume control dvol7 dvol 6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 10h signal select 4 0 lovl lp 0 0 0 lin 0 11h digital filter select 1 0 0 lpf hpf 0 0 0 1 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 0 0 0 0 0 14h reserved 0 0 0 0 0 0 0 0 15h reserved 0 0 0 0 0 0 0 0 16h reserved 0 0 0 0 0 0 0 0 17h reserved 0 0 0 0 0 0 0 0 18h reserved 0 0 0 0 0 0 0 0 19h reserved 0 0 0 0 0 0 0 0 1ah reserved 0 0 0 0 0 0 0 0 1bh reserved 0 0 0 0 0 0 0 0 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h beep frequency bpcnt 0 0 0 0 0 bpfr1 bpfr0 21h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 22h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 23h beep repeat count 0 bptm6 b ptm5 bptm4 bptm3 bptm2 bptm1 bptm0 24h beep vol/control bpout 0 0 0 0 bplvl2 bplvl1 bplvl0 25h reserved 0 0 0 0 0 0 0 0 26h reserved 0 0 0 0 0 0 0 0 27h digital mic 0 0 0 pmdm dclke dmpe dclkp dmic 28h beep mode select 0 0 0 0 0 0 bpm1 bpm0 29h noise suppression 1 0 nsce nst hh1 nsthh0 nsthl3 nsthl2 nsthl1 nsthl0 2ah noise suppression 2 0 0 natt1 natt0 0 0 nsgain1 nsgain0 2bh noise suppression 3 nsref7 nsref6 ns ref5 nsref4 nsref3 nsre f2 nsref1 nsref 0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8
[ak4636] ms1012-e-01 2010/08 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5 a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 the pdn pin = ?l? resets the registers to their default values. note 43. the bits defined as 0 must contain a ?0? value. note 44. the bits defined as 1 must contain a ?1? value. note 45. reading of address 12h ~ 1bh, 25h ~ 26h and 31h ~ 4fh are not possible. note 46. 0fh and 0dh are for address read only. writi ng access to 0dh and 0fh does not effect the operation.
[ak4636] ms1012-e-01 2010/08 - 73 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm pmbp pmspk pmao pmdac 0 pmadc r/w r/w r/w r/w r/w r/w r/w r r/w default 0 0 0 0 0 0 0 0 pmadc: adc block power control 0: power down (default) 1: power up when the pmadc bit changes from ?0 ? to ?1?, the initialization cycle (1059/fs=133ms@8khz) starts. after initializing, digital data of the adc is output. pmdac: dac block power control 0: power down (default) 1: power up pmao: mono line out power control 0: power down (default) 1: power up pmspk: speaker amplifier power control 0: power down (default) 1: power up pmbp: beep input power management 0: power down (default) 1: power up when pmbp bit = ?0?, the path fro m beep to speaker is still connected . set beeps bit = ?0? to disconnect this path. the path from beep to mono lineout is the same. it can be disc onnected by setting beepa bit = ?0?. pmvcm: vcom block power control 0: power down (default) 1: power up pmpfil: programmable filter block (hpf/ lpf/ 5-band eq/ alc) power control 0: power down (default) 1: power up all blocks can be powered-down by writing ?0? to the address ?00h?, pmpll, pmv, pmmp, pmdm, dmpe and mcko bits. in this case, register values are maintained. pmvcm bit must be ?1? when one of bocks is powered- up. pmvcm bit can only be ?0? when the address ?00h? and all power management bits (pmpll, pmv, pmmp, pmdm, dmpe and mcko) are ?0?. when using either adc, dac, digital microphone or progr ammable filter (pmadl bit = ?1?, pmdm bit =?1?, pmdac bit = ?1? or pmpfil bit = ?1?), clock must be supplied.
[ak4636] ms1012-e-01 2010/08 - 74 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 pm v 0 0 0 m/s 0 mcko pmpll r/w r/w r r r r/w r r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll block po wer control select 0: pll is power down and exte rnal is selected. (default) 1: pll is power up and pll mode is selected. mcko: master clock output enable 0: ?l? output (default) 1: 256fs output m/s: select master/ slave mode 0: slave mode (default) 1: master mode pmv: video block power control 0: power down (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 sppsn beeps dacs daca mgain3 pmmp mgain2 mgain0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain3-2, mgain0: mic-amp gain control ( table 20 ) mgain1 bit is located at d5 bit of 03h. default: ?0001? (+20.0db) pmmp: mpi pin power control 0: off (default) 1: on daca: switch control from dac to mono line amp 0: off (default) 1: on when pmao bit is ?1?, daca bit is enabled. when pmao bit is ?0?, the aout pin goes vss1. dacs: switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. beeps: switch control from min pin to speaker-amp 0: off (default) 1: on when beeps bit is ?1?, mono signal is input to speaker-amp. sppsn: speaker-amp power-save mode 0: power-save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is on power-save mode. in this mode, the spp pin goes to hi-z and outputs svdd/2 voltage. when pmspk bit = ?1?, sppsn bit is enabled. after the pdn pin is set to ?l?, speaker-amp is in power-down mode since pmspk bit is ?0?.
[ak4636] ms1012-e-01 2010/08 - 75 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 pfsdo aops mgain1 spkg1 spkg0 beepa pfdac adcpf r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 adcpf: select input signal to programmable filter/alc. 0: sdti 1: output of adc (default) pfdac: select input signal to dac. 0: sdti (default) 1: output of programmable filter/alc beepa: switch control of beep signal to mono-amp 0: off (default) 1: on when pmao bit=?1?, this bit is enabled. when pmao bit=?0?, aout pin goes to vss1. spkg1-0: select speaker-amp output gain ( table 55 ) default: ?00? figure 65. speaker and mono lineout-amps switch control mgain1: mic-amplifier gain control ( table 20 ) mgain3-2 and mgain0 bits are d3, d1 and d0 of 02h. default: ?0001? (+20.0db) dac spk dacs aout beep beeps daca beepa
[ak4636] ms1012-e-01 2010/08 - 76 - aops: mono line output power-save mode 0: normal operation (default) 1: power-save mode power-save mode is enable at aops bit = ?1?. pop noi se at power-up/down can be reduced by changing at pmao bit = ?1?. ( figure 52 ) pfsdo: select of signal from sdto 0: output of adc (1 st - hpf) 1: output of programmable filter/alc (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 1 1 0 dif1-0: audio interface format ( table 16 ) default: ?10? (msb first) bcko1-0: select bick output frequency at master mode ( table 9 ) default: ?01? (32fs) pll3-0: select input frequency at pll mode ( table 4 ) default: ?0000? (fck pin) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 adrst fcko fs3 msbs bckp fs2 fs1 fs0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: setting of sampling frequency ( table 5 and table 6 ) and mcki frequency ( table 11 ) these bits select sampling frequency at pll mode and mcki frequency at ext mode. default: ?0000? bckp, msbs: ?00? (default) ( table 17 ) fcko: select fck output frequency at master mode ( table 10 ) default: ?0? adrst: initialization cycle setting of adc 0: 1059/fs (default) 1: 291/fs
[ak4636] ms1012-e-01 2010/08 - 77 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select 0 wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 wtm2-0: alc1 recovery waiting period ( table 30 ) a period of recovery operation when any limiter ope ration does not occur during the alc1 operation. default is ?000?. ztm1-0: alc1, alc2, ivol and ovol zero crossing timeout period ( table 29 ) the gain is changed by the manual volume controlling (a lc off) or the recovery operation (alc on) only at zero crossing or timeout. the default value is ?00?. rfst1-0 : alc first recovery speed ( table 34 ) default: ?00? (4times) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 lmth1-0: alc limiter detection level / recovery waiting counter reset level ( table 27 ) lmth1 bit is located at d6 bit of 0bh. default: ?01? rgain1-0: alc recovery gain step ( table 31 ) rgain1 bit is located at d7 bit of 0bh. default: ?00? lmat1-0: alc limiter att step ( table 28 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc1: alc of recoding path enable 0: disable (default) 1: enable alc2: alc2 of playback path enable 0: disable (default) 1: enable lfst: limiter function of alc when the output is bigger than fs. 0: the volume value is changed at zero crossing or timeout. (default) 1: when output of alc is bigger than fs, vol value is changed instantly.
[ak4636] ms1012-e-01 2010/08 - 78 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 0 0 0 1 0 1 iref7-0: reference value at alc recovery ope ration for recoding. (0.375db step, 242 level) ( table 32 ) default: ?c5h? (+19.5db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h input digital volume control ivol7 ivol6 ivol5 ivol4 ivol3 ivol2 ivol1 ivol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ivol7-0: input digital volume; 0.375db step, 242 level ( table 22 ) default: ?91h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah digital volume control ovol7 ov ol6 ovol5 ovol4 ovol3 ovol2 ovol1 ovol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ovol7-0: output digital volume; 0.375db step, 242 level ( table 23 ) default: ?91h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 1 0 1 0 0 0 oref5-0: reference value at alc recovery operation for playback. 1.5db step, 60 level ( table 33 ) default: ?28h? (+6.0db) lmth1-0: alc limiter detection level / recovery waiting counter reset level ( table 27 ) lmth0 bit is located at d0 bit of 07h. default: ?01? rgain1-0: alc recovery gain step ( table 31 ) rgain0 bit is located at d1 bit of 07h. default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch video mode control 0 0 0 vgca4 vgca3 vgca2 vgca1 vgca0 r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 1 0 vgca4-0: gain control of video output ( table 56 ) default: ?00010?
[ak4636] ms1012-e-01 2010/08 - 79 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh input digital volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 r/w r r r r r r r r default - - - - - - - - vol7-0: the current volume of alc; 0.375db step, 242 level, read only ( table 35 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 datt1 datt0 smute mdif 0 0 0 read r/w r/w r/w r/w r/w r r r r/w default 0 0 0 0 0 0 0 0 read: read function enable 0: disable (default) 1: enable mdif: single-ended / full-differential input select 0: single-ended input (mic pin or lin pin: default) 1: full-differential input (mic/micp and lin/micn pins) smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted datt1-0: output digital volume2; 6db step, 4 level ( table 24 ) default: ?00h? (0.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh thermal shutdown dvol7 dvol6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 1 0 1 0 1 dvol7-0: output digital vo lume3; linear step ( table 25, table 26 ) default: ?f5h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h signal select 4 0 lovl lp 0 0 0 lin 0 r/w r r/w r/w r r r r/w r default 0 0 0 0 0 0 0 0 lin: select input data of adc 0: mic pin (default) 1: lin pin lp: low power mode 0: normal mode (default) 1: low power mode: it can be operated by fs=22.05khz or less. lovl: lineout gain setting 0: 0db(default) 1: +3db
[ak4636] ms1012-e-01 2010/08 - 80 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select 1 0 0 lpf hpf 0 0 0 1 r/w r r r/w r/w r r r r default 0 0 0 1 0 0 0 1 hpf: hpf2 enable 0: disable 1: enable (default) when hpf bit is ?0?, hpf2 block is bypassed (0db). when hpf bit is ?1?, f1a13- 0, f1b13-0 bits are enabled. lpf: lpf coefficient setting enable 0: disable (default) 1: enable when lpf bit is ?0?, lpf block is bypassed (0db). when lpf bit is ?1?, f2a13-0, f2b13-0 bits are enabled. addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 r/w w w w w w w w w default f1a13-0 bits = 0x1f16, f1b13-0 bits = 0x1e2b f1a13-0, f1b13-0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: f1a13-0 bits = 0x1f16, f1b13-0 bits = 0x1e2b fc = 75hz@fs = 8khz, 150hz@fs = 16khz addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h beep frequency bpcnt 0 0 0 0 0 bpfr1 bpfr0 r/w r/w r r r r r r/w r/w default 0 0 0 0 0 0 0 0 bpfr1-0: beep signal output frequency setting ( table 47 , table 48 , table 49 ) default: ?00h? bpcnt: beep signal output mode setting 0: once output mode. (default) 1: continuous mode in continuous mode, the beep signal is output while bpcnt bit is ?1?. in once output mode, the beep signal is output by only the frequency set with bptm6-0 bits.
[ak4636] ms1012-e-01 2010/08 - 81 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 21h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpon7-0: setting on-time of beep signal output ( table 50 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpoff7-0: setting off-time of beep signal output ( table 51 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 23h beep repeat count 0 bptm6 b ptm5 bptm4 bptm3 bptm2 bptm1 bptm0 r/w r r/w r/w r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 bptm6-0: setting the number of times that beep signal repeats ( table 52 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 24h beep vol/control bpout 0 0 0 0 bplvl2 bplvl1 bplvl0 r/w r/w r r r r r/w r/w r/w default 0 0 0 0 0 0 0 0 bplvl2-0: setting output level of beep signal ( table 53 ) default: ?0h? (0db) bpout: beep signal control 0: off (default) 1: on at the time of bpcnt = ?0?, when bp out bit is ?1?, the beep signal starts outputting. the beep signal stops after the number of times that is set by bptm6-0 bit, and bpout bit is set to ?0? automatically. addr register name d7 d6 d5 d4 d3 d2 d1 d0 27h digital mic 0 0 0 pmdm dclke dmpe dclkp dmic r/w r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dmic: digital microphone connection select 0: analog mic (set to mic/lin pin or micp/micn pin: default) 1: digital mic (set to dmdat pin/ dmclk pin)
[ak4636] ms1012-e-01 2010/08 - 82 - dclkp: data latching edge select 0: data is latched on the dmclk rising edge (? ?). (default) 1: data is latched on the dmclk falling edge (? ?). dmpe: digital microphone power supply 0: externally (the same supply as avdd) (default) 1: dmp pin dclke: dmclk pin output clock control 0: ?l? output (default) 1: 64fs output pmdm: digital microphone power management 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 28h beep mode select 0 0 0 0 0 0 bpm1 bpm0 r/w r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 bpm1-0: beep mode setting ( table 43 ) default: ?00?: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 29h noise suppression 1 0 nsce nsthh1 nsthh0 nsthl3 nsthl2 nsthl1 nsthl0 r/w r r/w r/w r/w r/ w r/w r/w r/w default 0 0 0 1 0 0 0 0 nsthl3-0: noise suppression threshold low level setting ( table 38 ) default: ?0000? (-81dbfs) nsthh1-0: noise suppression threshold high level setting( table 40 ) default: ?01? (nsthl3-0 bits + 6db) nsce: noise suppression enable 0: disable (default) 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 2ah noise suppression 2 0 0 na tt1 natt0 0 0 nsgain1 nsgain0 r/w r r r/w r/w r r r/w r/w default 0 0 0 1 0 0 0 1 nsgain1-0: alc first recovery speed setting after noise suppression ( table 41 ) default: ?01? (12 times) natt1-0: noise attenuate step setting ( table 39 ) default: ?01? (1/2 step)
[ak4636] ms1012-e-01 2010/08 - 83 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 2bh noise suppression 3 nsref7 nsref6 ns ref5 nsref4 nsref3 ns ref2 nsref1 nsref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 nsref7-0: reference level setting at noise suppression 0.375db step, 242 level ( table 42 ) default: ?91h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f2a13-0, f2b13-0: lpf coefficient (14bit x 2) default: ?0000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when eq1 bit is ?1?, e1a15-0, e1b15-0, e1c15-0 bits are enabled. when eq1 bit is ?0?, eq1 block is through (0db). eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit is ?1?, e2a15-0, e2b15-0, e2c15-0 bits are enabled. when eq2 bit is ?0?, eq2 block is through (0db). eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit is ?1?, e3a15-0, e3b15-0, e3c15-0 bits are enabled. when eq3bit is ?0?, eq3 block is through (0db). eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit is ?1?, e4a15-0, e4b15-0, e4c15-0 bits are enabled. when eq4 bit is ?0?, eq4 block is through (0db). eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when eq5 bit is ?1?, e5a15-0, e5b15-0, e5c15-0 bits are enabled. when eq5 bit is ?0?, eq5 block is through (0db).
[ak4636] ms1012-e-01 2010/08 - 84 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ?0000h? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ?0000h? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ?0000h? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ?0000h? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ?0000h?
[ak4636] ms1012-e-01 2010/08 - 85 - system design figure 66 ~ figure 69 show the system connection diagram. the evaluation board [akd4636] demonstrates the optimum layout, power supply arrangements and measurement results. < mic single-end input > ak4636ecb top vie w avdd svdd mcko analog supply 2.8 3.6v 0.1 2.2k speaker cp 0.1 dsp & p vss1 vin vcoc csn vout vvdd vcom mpi cclk cdtio i2c mic lin beep aout fck mcki bick spp vss2 dvdd pdn spn vss3 sdti sdto rp 75 + 10 0.1 + 2.2 c 1 220 20 k 0.1 10 c 0.1 0.1 ri ci analog ground digital ground figure 66. typical connection diagram (3-wire mode, i2c pin = ?l?, bpm1-0 bits = ?10?) notes: - vss1, vss2 and vss3 of the ak4636 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 4 . - when the ak4636 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to fck and bick pins of the ak4636. -when avdd, dvdd, svdd and vvdd we re distributed, avdd = 2.6 ~ 3.6v, dvdd = 1.6 ~ 3.6v, svdd = 2.6 ~ 3.6v, vvdd = 2.8 ~ 3.6v. -1st-oder hpf consists of the input impedance of the lin pin and min pin (r = typ 30 k ) and the lin, min pin capacitors ?c? before mic-amp. the cut-off frequency of the hpf(fs) is calculated by the following formula. fc = 1 / (2 r c)
[ak4636] ms1012-e-01 2010/08 - 86 - AK4636EN nc nc vss3 beep a out lin mic mpi spn svdd spp nc vss2 dvdd mcko pdn vcom vcoc a vdd vss1 vvdd vout vin i2c sdto sdti bick mcki fck cclk/ scl cdtio csn/ sda a k4636en top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 20 k 0.1u rp power supply 2.8 3.6v 0.1u 10 dsp & p speaker cp 10u analog ground digital ground 0.1u 1u 220 2.2k c c ri ci 0.1u 0.1u 2.2u 0.1u 75 figure 67. typical connection diagram (3-wire mode, i2c pin = ?l?, bpm1-0 bits = ?10?) notes: - vss1, vss2 and vss3 of the ak4636 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 4 . - when the ak4636 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to fck and bick pins of the ak4636. -when avdd, dvdd, svdd and vvdd we re distributed, avdd = 2.6 ~ 3.6v, dvdd = 1.6 ~ 3.6v, svdd = 2.6 ~ 3.6v, vvdd = 2.8 ~ 3.6v. -1st-oder hpf consists of the input impedance of the lin pin and min pin (r = typ 30 k ) and the lin, min pin capacitors ?c? before mic-amp. the cut-off frequency of the hpf(fs) is calculated by the following formula. fc = 1 / (2 r c)
[ak4636] ms1012-e-01 2010/08 - 87 - < mic differential input > ak4636ecb top vie w avdd svdd mcko analog supply 2.8 3.6v 0.1 1k speaker cp 0.1 dsp & p vss1 vin vcoc csn vout vvdd vcom mpi cclk cdtio i2c micp micn beep aout fck mcki bick spp vss2 dvdd pdn spn vss3 sdti sdto rp 75 + 10 0.1 + 2.2 c 1 220 20k 0.1 10 c 0.1 0.1 ri ci 1k analog ground digital ground figure 68. typical connection diagram (3-wire mode, i2c pin = ?l?, bpm1-0 bits = ?10?) notes: - vss1, vss2 and vss3 of the ak4636 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 4 . - when the ak4636 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to fck and bick pins of the ak4636. -when avdd, dvdd, svdd and vvdd we re distributed, avdd = 2.6 ~ 3.6v, dvdd = 1.6 ~ 3.6v, svdd = 2.6 ~ 3.6v, vvdd = 2.8 ~ 3.6v. -1st-oder hpf consists of the input impedance of the micp pin and micn pin (r = typ 30 k ) and the micp, micn pin capacitors ?c? before mi c-amp. the cut-off frequency of the hpf(fs) is calculated by the following formula. fc = 1 / (2 r c)
[ak4636] ms1012-e-01 2010/08 - 88 - AK4636EN nc nc vss3 beep a out micn micp mpi spn svdd spp nc vss2 dvdd mcko pdn vcom vcoc a vdd vss1 vvdd vout vin i2c sdto sdti bick mcki fck cclk/ scl cdtio csn/ sda a k4636en top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 20 k 0.1u rp power supply 2.8 3.6v 10 dsp & p speaker cp 10u analog ground digital ground 0.1u 1u 220 1k c c ri ci 0.1u 0.1u 2.2u 0.1u 75 1 k 0.1u figure 69. typical connection diagram (3-wire mode, i2c pin = ?l?, bpm1-0 bits = ?10?) notes: - vss1, vss2 and vss3 of the ak4636 should be distributed separately from the ground of external controllers. - all digital input pins except pull-down pin should not be left floating. - in ext mode (pmpll bit = ?0?), rp and cp of the vcoc pin can be open. - in pll mode (pmpll bit = ?1?), rp and cp of the vcoc pin should be connected as shown in table 4 . - when the ak4636 is used at master mode, fck and bick pins are floating before m/s bit is changed to ?1?. therefore, a pull-up resistor with around 100 ? should be connected to fck and bick pins of the ak4636. -when avdd, dvdd, svdd and vvdd we re distributed, avdd = 2.6 ~ 3.6v, dvdd = 1.6 ~ 3.6v, svdd = 2.6 ~ 3.6v, vvdd = 2.8 ~ 3.6v. -1st-oder hpf consists of the input impedance of the micp pin and micn pin (r = typ 30 k ) and the micp, micn pin capacitors ?c? before mi c-amp. the cut-off frequency of the hpf(fs) is calculated by the following formula. fc = 1 / (2 r c)
[ak4636] ms1012-e-01 2010/08 - 89 - r and c of vcoc pin ( note 32 ) mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 10ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 10ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 10ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 10ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 10ms others others n/a note 32. the tolerance of r is 5%, the tolerance of c is 30% table 4. setting of pll mode (*fs: sampling frequency, n/a: not available) 1. grounding and power supply decoupling the ak4636 requires careful attention to power s upply and grounding arrangements. avdd, dvdd, svdd and vvdd are usually supplied from the system?s analog supply. if avdd, dvdd, svdd and vvdd are supplied separately, the power up sequence is not critical but the pdn pin must be put ?l? after all powers are supplied. vss1, vss2 and vss3 of the ak4636 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4636 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4636. 3. analog inputs the microphone input supports both single-ended and diffe rential inputs. the input signal range is 1.5vpp (typ)@mgain = 0db or 0.15vpp (typ)@mgain = +20db entered around the internal common voltage 1.15v (typ). usually the input signal is ac coupled with a capacitor. the cut-off frequency is fc =1/ (2 rc). the ak4636 can accept input voltages from vss to avdd. 4. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). the ideal output is vcom voltage for 0000h (@16bit). mono line output from the aout pin is 1.5vpp (typ)@lovl bit = ?0? centered around common voltage 1.15v (typ). 5. video inputs video inputs are ac coupled with a 0.1uf capacitor. this ac coupling capacitor must be 0.1uf (in 30% tolerance). attention should be given to avoid coupli ng with other analog and digital signals. 6. video outputs the ak4636 integrates 2ch video amp for driving 150 ? resistance. the gain of each amp is +6db@gca=0db (typ)
[ak4636] ms1012-e-01 2010/08 - 90 - control sequence clock set up when adc, dac, digital microphone a nd programmable filter are used, the clocks must be supplied. 1. pll master mode bick pin fck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 20msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) 1msec (max) (7) mcko pin output (9) (8) 20msec(max) example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 12mhz mcko : enable sampling frequency:48khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:01h addr:04h, data:6ah addr:05h, data:23h (4)addr:01h, data:0bh mcko, bick and fck output figure 70. clock set up sequence (1) (1) after power up, pdn pin = ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the ak4636. (2) dif1-0, pll3-0, fs3-0, bcko1-0, msbs, bckp and m/s bits must be set during this period. (3) power up vcom: pmvcm bit = ?0? ?1? vcom should first be powered-up be fore the other block operates. (4) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (5) pll lock time is 20ms(max) after pmpll bit changes from ?0? to ?1? and mcki is supplied from an external source. (6) the ak4636 starts to output the fck and bick clocks after the pll becomes stable and the normal operation starts. (7) the invalid frequencies are output from fck and bick pins during this period. (8) the invalid frequency is output from the mcko pin during this period. (9) the normal clock is output from the mcko pin after the pll is locked.
[ak4636] ms1012-e-01 2010/08 - 91 - 2. when the external clock (fck or bick pin) is used in pll slave mode. pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) fck pin bick pin (4) (5) input 4fs of example: audio i/f format: dsp mode bckp = msbs = ?0? pll reference clock: bick bick frequency: 64fs sampling frequency: 48khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:38h addr:05h, data:20h (4) addr:01h, data:01h bick and fck input figure 71. clock set up sequence (2) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the ak4636. (2) dif1-0, fs3-0, pll3-0, msbs and bckp bits must be set during this period. (3) power up vcom: pmvcm bit = ?0? ?1? vcom should first be powered up be fore the other block operates. (4) pll starts after the pmpll bit cha nges from ?0? to ?1? and pll referen ce clocks (fck or bick pin) are supplied. pll lock time is 160ms(max) when pll reference clock is fck, and pll lock time is 2ms(max) when pll reference clock is bick. (5) normal operation starts after the pll is locked.
[ak4636] ms1012-e-01 2010/08 - 92 - 3. when the external clock (mcki pi n) is used in pll slave mode. bick pin fck pin pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 20msec(max) (8) input example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 12mhz mcko : enable sampling frequency:48khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:04h, data:68h addr:05h, data:23h (4)addr:01h, data:03h mcko output start bick and fck input start figure 72. clock set up sequence (3) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the ak4636. (2) dif1-0, pll3-0, fs3-0, bcko1-0, msbs, bckp and m/s bits must be set during this period. (3) power up vcom: pmvcm bit = ?0? ?1? vcom should first be powered up before the other block operates. (4) pll power up: pmpll bit ?0? ?1? (5) pll lock time is 20ms(max) after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (mcki pin) is supplied. (6) normal clock is output from the mcko pin after pll is locked. (7) the invalid frequency is output from the mcko pin during this period. (8) bick and fck clocks should be synchronized with mcko clock.
[ak4636] ms1012-e-01 2010/08 - 93 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) fck pin bick pin (5) input pmpll bit (addr:01h, d0) "l" (5) mcki pin input (4) example audio i/f format:msb justified (adc and dac) input mcki frequency: 256fs sampling frequency:48khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:00h mcki, bick and fck input figure 73. clock set up sequence (4) (1) after power up: pdn pin ?l? ?h? ?l? time (1) of 150ns or more is needed to reset the ak4636. (2) dif1-0 and fs1-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ?1? vcom should first be powered up before the other block operates. (4) power down pll: pmpll bit = ?0? (5) normal operation starts after the mcki, fck and bick are supplied.
[ak4636] ms1012-e-01 2010/08 - 94 - digital mic inputs fs3-0 bits (addr:05h, d5,d2-0) digital mic control (addr:27h, d3-0) pmpfil bit (addr:00h, d7) pmdm bit (addr:27h, d4) sdto pin state 0,010 x,xxx xxh 0bh o data output normal data ouput (1) (2) (10) alc1 state alc1 enable alc1 disable (6) alc1 control 1 (addr:06h) xxh 14h (3) alc1 control 2 (addr:08h) xxh c5h (4) alc1 control 3 (addr:07h) xxh a1h ivol7-0 bits (addr:09h) xxh c5h (5) (7) signal select (addr:03h) xxh 81h filter co-ef (addr:10h-1f) xx....x xx....x filter select (addr:11h d5-4, d0) xx1 011 (8) (9) o data output (11) (13) (12) alc1 disable initialize 291/fs or 1059/fs adrst bit (addr:05h, d7) x x example: pll master mode audio i/f format: msb justified sampling frequency: 16khz digital mic setting: d ata is latched on the dmclk failing edge digital mic power supply ?extenally? alc1 setting:refer to table 36 hpf : on (fc=150hz) 4+1 band eq : off (2) addr:27h, data:0bh ( 3 ) addr:06h, data:14h ( 1 ) addr:05h, data:02h (4) addr:08h, data:c5h ( 5 ) addr:09h, data:c5h (6) addr:07h, data:a1h ( 7 ) addr:03h, data:81h ( 8-1 ) addr:1ch, data:a9h (8-2) addr:1dh, data:1fh ( 8-3 ) addr:1eh, data:53h ( 8-4 ) addr:1fh, data:1fh (9) addr:11h, data:11h ( 10 ) addr:00h, data:80h recording ( 12 ) addr:27h, data:0bh ( 11 ) addr:27h, data:1bh ( 13 ) addr:00h, data:00h figure 74. digital mic input recording sequence this sequence is an example of alc1 setting at fs=16khz. if the parameter of the alc1 is changed, please refer to the figure 47 . at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bit) and the initializing cycle of programmable filter (adrst bit). when the ak4636 is in pll mode, mic and programmable filter should be powered-up in consideration of pll lock time after the sampling frequency is changed. (2) set up digital mic(address 27h) (3) set up timer select for alc1 (addr: 06h) (4) set up ref value for alc1 (addr: 08h) (5) set up ivol value for alc1 (addr: 09h) (6) set up lmth0, rgain0, lmat1-0, zelm and alc1 bits (addr: 07h) (7) set up programmable filter path: pfsdo bit = adcpf bit = ?1? (8) set up coefficient of the programmable filter (hpf/eq) addr: 1ch ~ 1fh, 2ch ~ 2fh, 32h ~ 4fh (9) switch on/off of the programmable filter (hpf/eq) (10) power-up programmable filter: pmpfil bit = ?0? ? ?1? (11) power-up digital mic: pmdm bit = ?0? ? ?1? the initializing cycle of the digital filter is 1059/ fs= 24ms@fs=44.1khz when adrst bit = ?0?, and 291/fs=18ms@16khz when adrst bit = ?1?. alc starts operating at the value set by ivol (5). (12) power-down digital mic: pmdm bit = ?1? ? ?0? (13) power-down programmable filter: pmpfil bit = ?1? ? ?0?
[ak4636] ms1012-e-01 2010/08 - 95 - mic input recording fs3-0 bits (addr:05h, d5,d2-0) mic control (addr:02h, d2-0 addr :03h, d5) pmadc bit (addr:00h, d0) pmpfil bit (addr:00h, d7) adc internal state 0,010 x,xxx xxxx 0,001 power down initialize normal state power down 291/fs or 1059/fs (1) (2) (10) (11) alc1 state alc1 enable alc1 disable alc1 disable (6) alc1 control 1 (addr:06h) xxh 14h (3) alc1 control 2 (addr:08h) xxh c5h (4) alc1 control 3 (addr:07h) xxh a1h ivol7-0 bits (addr:09h) xxh c5h (5) (7) signal select (addr:03h) xxh 81h adrst bit (addr:05h, d7) filter co-ef (addr:10h-1f) xx....x xx....x filter select (addr:11h d5-4, d0) xx1 011 (8) (9) x x example: pll mast er mode audio i/f format: msb justified sampling frequency: 16khz pre mic am p:+20db mic power on adc initialize time: 291/fs alc1 setting:refer to table 36 hpf : on (fc=150hz) 4+1 band eq : off (2) addr:02h, data:05h ( 3 ) addr:06h, data:14h ( 1 ) addr:05h, data:02h (4) addr:08h, data:c5h ( 5 ) addr:09h, data:c5h (6) addr:07h, da t a:a1h ( 7 ) addr:03h, data:81h ( 8-1 ) addr:1ch, data:a9h (8-2) addr:1dh, data:1fh ( 8-3 ) addr:1eh, data:53h ( 8-4 ) addr:1fh, data:1fh (9) addr:11h, data:11h ( 10 ) addr:00h, data:c1h recordin g ( 11 ) addr:00h, data:40h figure 75. mic input recording sequence this sequence is an example of alc1 setting at fs=16khz. if the parameter of the alc1 is changed, please refer to the figure 47 . at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bit). when the ak4636 is in pll mode, programmable filter and adc should be powered-up in consideration of pll lock time after the sampling frequency is changed. (2) set up mic input (addr: 02h) (3) set up timer select for alc1 (addr: 06h) (4) set up ref value for alc1 (addr: 08h) (5) set up ivol value for alc1 (addr: 09h) (6) set up lmth0, rgain0, lmat1-0, zelm and alc1 bits (addr: 07h) (7) set up programmable filter path: pfsdo bit = adcpf bit = ?1? (8) set up coefficient of the programmable filter (hpf/eq) addr: 1ch ~ 1fh, 2ch ~ 2fh, 32h ~ 4fh (9) switch on/off of the programmable filter (10) power-up of the adc and programmable filter: pmpfil bit = pmadc bit = ?0? ? ?1? the initialization cycle of the adc is 1059/fs =24ms@fs=44.1khz when adrst bit = ?0?, 291/fs=18ms@fs=16khz when adrst bit= ?1?. alc star ts operating at the value set by ivol (5). (11) power-down of the adc and programmable filter: pmpfil bit = pmadc bit = ?1? ? ?0?
[ak4636] ms1012-e-01 2010/08 - 96 - mono lineout fs3-0 bits (addr:05h, d5, d2-0) ovol7-0 bits (addr:0ah, d7-0) pmdac bit (addr:00h, d2) pmao bit (addr:00h, d3) 0,010 x,xxx xxh 91h aout pin (1) (6) (2) daca bit (addr:02h, d4) (11) normal output (8) aops bit (addr:03h, d6) (7) >300 ms (9) (10) >300 ms (12) (4) alc2 control (addr:07h) (3) adcpf bit (addr:03h, d0) pfdac bit (addr:03h, d1) 0 or 1 0 0 or 1 1 0 or 1 0 (5) pmpfil bit (addr:00h, d7) example: pll master mode audio i/f format: msb justified samp ling frequency: 16 khz lovl bit = ?0? alc2 : off, ovol = ?91h ? alc 2 setting:refer to table 33 hpf : on (fc=15 0hz) 4+1 ban d eq : off (1) addr:05h, data:02h (2) addr:02h, data:10h (3) addr:03h, data:02h (4) addr:07h, data:00h (5) addr:0ah, data:91h (6) addr:03h, data:42h (7) addr:00h, data:cch (8) addr:03h, data:02h playback (9) addr:03h, data:42h (10) addr:00h, data:40h (11) addr:02h, data:00h (12) addr:03h, data:02h figure 76. mono lineout sequence in case of using digital volume in manual mode at first, clocks should be supplied according to ?clock set up? sequence. (1) set up the sampling frequency (fs3-0 bits). when th e ak4636 is pll mode, dac should be powered-up in consideration of pll lock time after the sampling frequency is changed. (2) set up the path of ?dac mono line amp? daca bit: ?0? ?1? (3) set up the path: adcpf bit = ?0?, pfdac bit = ?1? (4) alc2 disable: alc2 bit = ?0? (5) set up the digital volume (addr: 0ah) (6) aout power save mode: aops bit: ?0? ?1? (7) power-up of dac, programmable filter and mono line amp: pmdac bit = pmpfil bit = pmao bit = ?0? ?1? aout pin goes to ?h?. it takes 300ms (max) when c = 1f (8) exit power save mode of aout: aops bit = ?1? ?0? set up aops bit after aout became ?h?, then the aout pin starts outputting data. (9) enter power save mode of aout: aops bit= ?0? ?1? (10) power ?down the dac, programmable filter and mono line amp: pmdac bit = pmpfil bit = pmao bit = ?1? ? ?0? the aout pin starts going to ?l?. it takes 300ms(max) when c = 1 p f. (11) disable the path of ?dac mono line amp?: daca bit= ?1? ?0? (12) exit power save mode of aout: aops bit=?1? ?0? set up aops bit after aout became ?l?.
[ak4636] ms1012-e-01 2010/08 - 97 - speaker-amp output example: pll master mode audio i/f format: msb justified sampling frequency: 16khz spkg bit = ?1? alc2 : on alc2 setting:refer to table 33 hpf : on (fc=150hz) 5 band eq : off (2) addr:02h, data:20h ( 3 ) addr:06h, data:14h ( 1 ) addr:05h, data:a2h (4) addr:08h, data:28h ( 5 ) addr:0ah, data:91h (6) addr:07h, data:c1h ( 7 ) addr:03h, data:0ah ( 8-1 ) addr:1ch, data:16h ( 8-2 ) addr:1dh, data:1fh (8-3) addr:1eh, data:2bh ( 8-4 ) addr:1fh, data:1eh ( 9 ) addr:11h, data:11h ( 10 ) addr:00h, data:d4h ( 11 ) addr:02h, data:a0h playback (12) addr:02h, data:20h ( 13 ) addr:02h, data:00h (14) addr:00h, data:40h figure 77. speaker-amp output sequence in case of fs=16khz. refer to the table 37 for changing alc2 parameter. at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4636 is pll mode, dac and speaker-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ?dac spk-amp?: dacs bit = ?0? ?1? (3) set up timer select for alc2 (addr: 06h) (4) set up ref value for alc2 (addr: 08h) (5) set up ovol value, rgain1 and lmth1 for alc2 (addr: 10h) (6) set up lmth0, rgain0, lmat1-0, zelm and alc2 bit (addr: 07h) (7) set up the programmable filter path and spk-amp gain: pfdac bit = ?1?, adcpf bit = ?0?, spkg bit = ?x? (8) set up coefficient of the programmable filter (hpf/eq) addr: 1c ~ 1fh, 2ch ~ 2fh, 32h ~ 4fh (9) switch on/off of the programmable filter (10) power-up of the dac, spk-amp and programmable filter: pmdac bit = pmspk bit = pmpfil bit = ?0? ?1? (11) enable speaker out put: sppsn bit = ?0? ?1? 1ms or more time is needed before setting sppsn bit = ?1?after setting pmspk bit = ?1?. (12) disable speaker out put: sppsn bit = ?1? ?0? (13) disable the path of ?dac spk-amp?: dacs bit = ?1? ?0?. (14) power down of the dac, spk-amp and programmable filter: pmdac bit = pmspk bit = pmpfil bit = ?1? ? ?0? fs3-0 bits (addr:05h, d5,d2-0) 0,010 x,xxx (1) (2) dacs bit (addr:02h, d3) pmpfil bit (addr:00h, d7) a lc2 state a lc2 enable a lc2 disable a lc2 disable (6) a lc2 control 1 (addr:06h) xxh 14h (3) a lc2 control 2 (addr:08h) xxh 28h (4) a lc2 control 3 (addr:07h) xxh c1h ovol7-0 bits (addr:0ah) xxh 91h (5) (7) signal select (addr:03h) xxh 0a filter co-e f (addr:1ch-1fh) xx....x xx....x filter select (addr:11h, d5-4, d0 ) xx, x x1, 1 (8) (9) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) spp pin normal output sppsn bit (addr:02h, d7) hi-z spn pin normal output (10) (11) (14) (12) (13) hi-z hi-z hi-z hi-z hi-z
[ak4636] ms1012-e-01 2010/08 - 98 - beep signal output from speaker-amp pmspk bit (addr:00h, d4) beep gen bits (addr:20-24h) bpout bit (addr:24h, d7) (2) (1) (4) (3) (6) sppsn bit (addr:00h, d4) (5) xxh 00h (4) example:default (1) addr:00h, data:50h (2) addr:20-24h, data:00h (3) addr:02h, data:80h beep signal output (4) addr:24h, data:80h addr:24h, data:00h (auto) (5) addr:02h, data:00h (6) addr:00h, data:40h figure 78. ?bepp generator ? speaker-amp? output sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) power up beep-generator and speaker-amp: pmspk bit = ?0? ?1? (2) set up beep generator (addr: 20h ~ 24h)(when repeat output time bpcnt bit = ?0?) (3) enable spk-amp out put: sppsn bit = ?0? ?1? (4) beep output: bpout bit= ?0? ?1? (after outputting data particular set times, bpout bit automatically goes to ?0?) (5) disable speaker out put: sppsn bit = ?1? ?0? (6) power down of the spk-amp: pmspk bit = ?1? ?0?
[ak4636] ms1012-e-01 2010/08 - 99 - video signal input and output pmv bit (addr:01h, d7) vout pin vss1 vss1 (2) (3) normal output vgca4-0 bits (addr:0ch, d4-0) 0,0010 x,xxxx (4) pmvcm bit (addr:00h, d6) clocks x 1 clocks can be stopped, if only video output is enabled. (1) example: audio function :no use pll master mode vgca : 0db (3) addr:01h, data:8bh video output (2) addr:0ch, data:02h (4) addr:01h, data:0bh (1) addr:00h, data:45h figure 79. video output sequence when only the video block is operated, the clocks are not needed to be supplied. (1) power up vcom: pmvcm bit = ?x? ?1? (2) set up the gca gain (vgca4-0 bits) (3) power up the video amp: pmv bit = ?0? ?1? the signal input to the vin pin is output from the vout pin. (4) power down of the video amp: pmv bit = ?1? ?0? the output from the vout pin will stop and goes to 0v. then vcom can be powered-down when not using any audio functions.
[ak4636] ms1012-e-01 2010/08 - 100 - stop of clock master clock can be stopped wh en adc, dac and programmable f ilter are not in operation. 1. pll master mode external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "h" or "l" example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 12mhz mcko : enable sampling frequency:48khz stop an external mcki (1) (2) addr:01h, data:08h figure 80. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop an external master clock 2. pll slave mode (fck, bick pin) external bick pmpll bit (addr:01h, d0) input (1) (2) external fck input (2) example audio i/f format: dsp mode bckp = msbs = ?0? pll reference clock: bick bick frequency: 64fs sampling frequency: 48kh z ( 1 ) addr:01h, data:00h ( 2 ) sto p the external clocks figure 81. clock stopping sequence (2) (1) power down of the pll: pmpll bit = ?1? ?0? (2) stop an external master clock
[ak4636] ms1012-e-01 2010/08 - 101 - 3. pll slave mode (mcki pin) external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 12mhz mcko : enable sampling frequency:48khz (1) addr:01h, data:00h (2) stop the external clocks figure 82. clock stopping sequence (3) (1) power down of the pll: pmpll bit = ?1? ?0? stop the mcko output: mcko bit = ?1? ?0? (2) stop an external master clock. 4. ext slave mode external fck input (1) external bick input (1) external mcki input (1) example audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 12mhz mcko : enable sampling frequency:48khz (2) stop the external clocks (1) addr:01h, data:00h figure 83. clock stopping sequence (4) (1) stop an external master clock. power down vcom should be powered-down after the master clock is stopped if clocks are supplied when all blocks except for vcom are powered-down. the ak4636 is also powered-down by the pdn pin = ?l?. in this case, the registers are initialized.
[ak4636] ms1012-e-01 2010/08 - 102 - package (ak4636ecb) 29pin csp: 2.5mm x 3.0mm 0.5 0.3 0.05 0.08 s s 0.05 ab s b m a 0.625 0.05 0.25 0.0 5 e dc b a 2.96 0.05 1 2 4 5 3 6 a b c d e top view bottom view 4636 xxxx 2.46 0.05 1 2 4 5 3 6 material & lead finish package material: epoxy resin, halogen (bromine and chlorine) free solder ball material: snagcu
[ak4636] ms1012-e-01 2010/08 - 103 - package (AK4636EN) 32pin qfn (unit: mm) 2.4 0.1 0.4 0.18 0.05 0.00 min 0.05 max 0.65 max 2.4 0.1 1 9 16 25 4.0 0.1 4.0 0.1 0.45 0.10 a b 0.05 m 0.08 8 32 17 24 pin #1 id exposed pad 0.40 0.10 0.22 0.05 c0.3 note: the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4636] ms1012-e-01 2010/08 - 104 - marking (ak4636ecb) 4636 xxxx a 1 ?4636?: market number xxxx: date code (4 digit) : pin #1 indication marking (AK4636EN) 4636 xxxx 1 xxxx: date code identifier (4 digit)
[ak4636] ms1012-e-01 2010/08 - 105 - revision history date (yy/mm/dd) revision reason page contents 09/02/27 00 first edition 10/08/19 01 error correction 46 transfer function was changed. ?h(z) = {1 + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) } x h 1 (z)? ?h(z) = {1 + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) } x {1+h 1 (z)}? important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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